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DATA SHEET
MOS INTEGRATED CIRCUIT
PD64084
THREE-DIMENSIONAL Y/C SEPARATION LSI WITH ON-CHIP MEMORY
DESCRIPTION
The PD64084 realizes a high precision Y/C separation by the three-dimension signal processing for NTSC signal. This product has the on-chip 4-Mbit memory for flame delay, a high precision internal 10-bit A/D converter and D/A converter, and adapting 10-bit signal processing (only for luminance signal) and high picture quality. The PD64084 is completely single-chip system of 3D Y/C separation. This LSI includes the Wide Clear Vision ID signal (Japanese local format) decoder and ID-1 signal decoder.
FEATURES
* *
On-chip 4-Mbit frame delay memory. 2 operation mode Motion adaptive 3D Y/C separation 2D Y/C separation + Frame recursive Y/C NR
* * * * *
Embedded 10-bit A/D converter (1ch), 10-bit D/A converters (2ch), and System clock generator. Embedded Y coring, Vertical enhancer, Peaking filter, and Noise detector. Embedded ID-1 signal decoder, and WCV-ID signal decoder. I2C bus control. Dual power supply of 2.5 V and 3.3 V. For digital : DVDD = 2.5 V For analog : AVDD = 2.5 V For DRAM : DVDDRAM = 2.5 V For I/O : DVDDIO = 3.3 V
ORDERING INFORMATION
Part number Package
Note1 Note2
PD64084GC-8EA-A PD64084GC-8EA-Y
100-pin plastic LQFP (fine pitch) (14 x 14 mm) 100-pin plastic LQFP (fine pitch) (14 x 14 mm)
Notes 1. Lead-free product 2. High-thermal-resistance product
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. S16021EJ2V0DS00 (2nd edition) Date Published March 2003 NS CP (K) Printed in Japan
The mark
shows major revised points.
2002
PD64084
PIN CONFIGURATION (TOP VIEW)
*
100-pin plastic LQFP (fine pitch) (14 x 14 mm)
PD64084GC-8EA-A PD64084GC-8EA-Y
DVDD TEST26 AVDD VCOMY VRTY VRBY VCLY AYI AGND AGND CBPY AYO ACO CBPC AVDD TEST25 TEST24 TEST23 TEST22 TEST21 TEST20 TEST19 TEST18 CSI KIL 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DGND TESTIC1 TESTIC2 TEST01 TEST02 TEST03 TEST04 TEST05 TEST06 TEST07 TEST08 TEST09 EXTALTF EXTDYCO0 EXTDYCO1 EXTDYCO2 EXTDYCO3 EXTDYCO4 EXTDYCO5 EXTDYCO6 EXTDYCO7 EXTDYCO8 EXTDYCO9 DGNDRAM DGNDRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DGND LINE ALTF DYCO9 DYCO8 DYCO7 DYCO6 DYCO5 DYCO4 DYCO3 DYCO2 DYCO1 DYCO0 DVDD NSTD ST1 ST0 RSTB CLK8 CKMD AVDD FSCI AGND AGND FSCO
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Data Sheet S16021EJ2V0DS
DVDDRAM DVDDRAM TEST10 TEST11 TEST12 DVDDIO TEST13 DGND AGND AGND XI XO AVDD DVDD TEST14 TEST15 TEST16 TEST17 RPLL SLA0 SCL SDA DGND AGND AVDD
PD64084
PIN NAME
ACO AGND ALTF AVDD AYI AYO CBPC CBPY CKMD CLK8 CSI DGND DVDD DVDDIO DVDDRAM DYCO0 to DYCO9 EXTALTF FSCI FSCO KIL LINE NSTD RPLL RSTB SCL SDA SLA0 ST1, ST0 TEST01 to TEST26 TESTIC1, TESTIC2 VCLY VRTY VRBY VCOMY XI XO : Analog C (Chroma) Signal Output : Analog Section Ground : Alternate Flag for Digital YC Output : Analog Section Power Supply : Analog Composite Signal Input : Analog Y (Luma) Signal Output : C-DAC Phase Compensation Output : Y-DAC Phase Compensation Output : Clock Mode Selection : 8fSC Clock Input / Output : Composite Sync. Input (Active-low) : Digital Section Ground : Digital Section Power Supply : Digital I/O Section Power Supply : Internal DRAM Section Power Supply : Digital YC Signal (Alternative) Input / Outputs : Extend Alternate Flag for Digital YC Output : fSC (Subcarrier) Input : fSC (Subcarrier) Output : Killer Selection : Inter-Line Separate Selection : Non Standard Detection Monitor : Testing Selection : System Reset (Active-low) : Serial Clock Input : Serial Data Input / Output : Slave Address Selection : Inner States Monitor : Testing Selection : IC Testing Section : Clamp Voltage Output for ADC : Top Voltage Reference Output for ADC : Bottom Voltage Reference Output for ADC : Common Mode Reference Output for ADC : X'tal input : X'tal output
EXTDYCO0 to EXTDYCO9 : Extend Digital YC Signal (Alternative) Input / Outputs
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Data Sheet S16021EJ2V0DS
PD64084
BLOCK DIAGRAM
SEL
10-bit Digital Comp. Input
4-Mbit Frame Memory
C Delay & C Noise Reducer Comp. Input Clamp 10-bit ADC 4fSC 8fSC
SEL
C Y-Coring Y Y-Peaking Y-Enhancer ID-1 Enc.
10-bit C-DAC 10-bit Y-DAC
SEL
C Output
Y/C Separator & Y Noise Reducer 3-Line Comb Filter Motion Detector 3-Line Comb Filter 3-Line Comb Filter
Y Output
8fSC PLL BPF 8-bit fSC DAC 20 MHz Ext. Sync. Separate fSC/227.5fH Dec. Sync. Separate
Digital YC Output
4fSC WCV-ID Dec. ID-1 Dec. Timing Generator Non-Std. Detector Power Down cont. I2C Bus I/F I2C Bus Line
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Data Sheet S16021EJ2V0DS
PD64084
TERMINOLOGY
This manual use the abbreviation listed below: ADC DAC LPF BPF : A/D (Analog to Digital) converter : D/A (Digital to Analog) converter : Low-pass filter : Band-pass filter : Luminance, or luminance signal
Y signal, or Luma fSC 4fSC 8fSC fH 910fH 1820fH fV NR YNR CNR WCV-ID ID-1
C signal, or Chroma : Color signal, or chrominance signal : Color subcarrier frequency = 3.579545 MHz : 4 times fSC, burst locked clock = 14.318180 MHz : 8 times fSC, burst locked clock = 28.636360 MHz : Horizontal sync frequency = 15.734 kHz : 910 times fH, line locked clock = 14.318180 MHz : 1820 times fH, line locked clock = 28.636360 MHz : Vertical sync frequency = 59.94 Hz : Noise reduction : Luminance (Y) noise reduction : Chrominance (C) noise reduction : Wide Clear Vision standard ID signal (Japan only) : ID signal of EIAJ CPR-1204
In the following diagrams, a serial bus register is enclosed in a box:
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Data Sheet S16021EJ2V0DS
PD64084
CONTENTS
1.
PIN FUNCTIONS .....................................................................................................................................................9 1.1 Pin Functions ..................................................................................................................................................9
2.
SYSTEM OVERVIEW ............................................................................................................................................11 2.1 Operation Modes ..........................................................................................................................................11 2.2 Filter Processing ...........................................................................................................................................12 2.3 System Delay ................................................................................................................................................12 2.4 Start-up of Power Supply and Reset.............................................................................................................13
3.
VIDEO SIGNAL INPUT BLOCK ............................................................................................................................14 3.1 Video Signal Inputs .......................................................................................................................................14 3.2 Pedestal Level Reproduction ........................................................................................................................14 3.3 Video Signal Input Level ...............................................................................................................................15 3.4 Pin Treatment................................................................................................................................................15 3.5 External ADC Connection Method ................................................................................................................16
4.
CLOCK/TIMING GENERATION BLOCK...............................................................................................................17 4.1 Sync Separator and Timing Generator .........................................................................................................17 4.2 Composite Sync Signal Input........................................................................................................................17 4.3 Horizontal/Burst Phase Detection Circuit......................................................................................................17 4.4 PLL Filter Circuit ...........................................................................................................................................17 4.5 Killer Detection Circuit...................................................................................................................................17 4.6 fSC Generator.................................................................................................................................................18 4.7 8fSC-PLL Circuit.............................................................................................................................................18 4.8 Pin Treatment................................................................................................................................................18
5.
COMB FILTER BLOCK .........................................................................................................................................19 5.1 Line Comb Filter............................................................................................................................................19 5.2 Frame Comb Filter ........................................................................................................................................19 5.3 Mixer Circuit ..................................................................................................................................................19 5.4 C Signal Subtraction .....................................................................................................................................19
6.
MOTION DETECTION BLOCK..............................................................................................................................20 6.1 Line Comb Filter............................................................................................................................................20 6.2 DY Detection Circuit ......................................................................................................................................20 6.3 DC Detection Circuit .....................................................................................................................................20 6.4 Motion Factor Generation Circuit ..................................................................................................................20 6.5 Forcible Control for The Motion Factor..........................................................................................................20
7.
YNR/CNR BLOCK .................................................................................................................................................21 7.1 YNR/CNR Processing...................................................................................................................................21 7.2 Nonlinear Filter..............................................................................................................................................21 7.3 YNR/CNR Operation Stop.............................................................................................................................21
6
Data Sheet S16021EJ2V0DS
PD64084
8. NONSTANDARD SIGNAL DETECTION BLOCK ................................................................................................. 22 8.1 Horizontal Sync Nonstandard Signal Detection............................................................................................ 22 8.2 Vertical Sync Nonstandard Signal Detection ................................................................................................ 22 8.3 Frame Sync Nonstandard Signal Detection.................................................................................................. 22 8.4 Forced Standard or Nonstandard Signal Control.......................................................................................... 22 8.5 Noise Level Detection................................................................................................................................... 22 9. WCV-ID DECODER / ID-1 DECODER BLOCK..................................................................................................... 23 9.1 WCV-ID Decoder .......................................................................................................................................... 23 9.2 ID-1 Decoder ................................................................................................................................................ 24 10. Y SIGNAL OUTPUT PROCESSING BLOCK........................................................................................................ 25 10.1 Y High-Frequency Coring Circuit ................................................................................................................. 25 10.2 Y Peaking Filter Circuit ................................................................................................................................ 26 10.3 Vertical Aperture Compensation Circuit ...................................................................................................... 26 10.4 Turning On/Off Y Peaking and Vertical Aperture Compensation ................................................................. 26 10.5 ID-1 Encoder ............................................................................................................................................... 26 11. C SIGNAL OUTPUT PROCESSING BLOCK........................................................................................................ 27 11.1 C Signal Delay Adjustment .......................................................................................................................... 27 11.2 BPF and Gain Processing ........................................................................................................................... 27 12. VIDEO SIGNAL OUTPUT BLOCK........................................................................................................................ 28 12.1 Digital YC Output Processing ...................................................................................................................... 28 12.2 Video Signal Output Level ........................................................................................................................... 28 12.3 Pin Treatment .............................................................................................................................................. 29 13. EXTEND DIGITAL INPUT / OUTPUT.................................................................................................................... 30 13.1 Usage of extend digital I/O terminals........................................................................................................... 30 13.2 Digital YC output format .............................................................................................................................. 30 13.3 Pin Treatment .............................................................................................................................................. 30 14. DIGITAL CONNECTION WITH GHOST REDUCER IC PD64031A................................................................... 31 14.1 Outline ......................................................................................................................................................... 31 14.2 System Configuration and Control Method.................................................................................................. 33 14.2.1 Selecting video signal input path...................................................................................................... 33 14.2.2 Selecting mode according to clock and video signal input path ....................................................... 33 14.3 Setting of Digital Direct-Connected System ................................................................................................ 34 14.3.1 Hardware setting .............................................................................................................................. 34 14.3.2 Register setting ................................................................................................................................ 35 15. I C BUS INTERFACE............................................................................................................................................. 36 15.1 Basic Specification ...................................................................................................................................... 36 15.2 Data Transfer Formats ................................................................................................................................. 37 15.3 Initialization.................................................................................................................................................. 38 15.4 Serial Bus Registers .................................................................................................................................... 39 15.5 Serial Bus Register Functions ..................................................................................................................... 41
2
7
Data Sheet S16021EJ2V0DS
PD64084
16. ELECTRICAL CHARACTERISTICS .....................................................................................................................57 17. APPLICATION CIRCUIT EXAMPLE .....................................................................................................................62 18. PACKAGE DRAWING............................................................................................................................................63 19. RECOMMENDED SOLDERING CONDITIONS.....................................................................................................64
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Data Sheet S16021EJ2V0DS
PD64084
1. PIN FUNCTIONS 1.1
No.
Pin Functions
Table 1-1. Pin Functions (1/2)
Symbol I/O Level Buffer type PU/PD [k] 3.3 V PD:50 Device test (Open) Digital section ground IC testing (Grounded) Description
1, 33, 48, 75 2, 3 4-12, 28-30, 78-85, 99 13 14 - 23 24, 25 26, 27 31 32, 40-43 34, 35 36 37 38 39, 62, 100 44 45 46 47 49 50 51 52, 53 54 55 56
DGND TESTIC1, TESTIC2 TEST01-TEST09, TEST10-TEST12, TEST18-TEST25, TEST26 EXTALTF EXTDYCO0EXTDYCO9 DGNDRAM DVDDRAM DVDDIO TEST13, TEST14-TEST17 AGND XI XO AVDD DVDD RPLL SLA0 SCL SDA AGND AVDD FSCO AGND FSCI AVDD CKMD
I
LVTTL
O I/O -
LVTTL LVTTL 3-state -
3.3 V 3 mA 3.3 V 3 mA -
Extended alternate flag output (This pin is enable in EXTDYCO = 1) Extended digital I/O (These pins are enable in EXTDYCO = 1) DRAM section ground DRAM section 2.5 V supply voltage I/O terminal section 3.3 V supply voltage Device Test (Grounded)
I O I I I I/O O I I
Analog Analog LVTTL LVTTL Schmitt Fail Safe Schmitt Fail Safe Analog Analog LVTTL 3.3 V PD:50 2.5 V 2.5 V 3.3 V 6 mA 3.3 V PD:50 3.3 V 3.3 V 2.5 V 2.5 V
-
X'tal oscillation circuit section gound fSC generator reference clock input (X'tal is connected.) fSC generator reference clock inverted output (X'tal is connected.)
-
X'tal oscillation circuit section 2.5 V supply voltage Digital section 2.5 V supply voltage Test pin (Grounded) I2C bus slave address selection input (L : B8h / B9h, H : BAh / BBh) I2C bus clock input (Connected to system SCL line) I2C bus data input/output (Connected to system SDA line)
-
fSC generator DAC section ground fSC generator DAC section 2.5 V supply voltage fSC generator fSC output
-
8fSC-PLL ground 8fSC-PLL fSC input
-
8fSC-PLL section 2.5 V supply voltage Clock mode test input (Grounded) ('L' : Normal mode, 'H' : 8fsc clock external input mode)
9
Data Sheet S16021EJ2V0DS
PD64084
Table 1-1. Pin Functions (2/2)
No. Symbol I/O Level Buffer type PU/PD [k] 3.3 V 6 mA 3.3 V PU:50 59 60 61 6372 ST0 ST1 NSTD DYCO0DYCO9 O O O I/O LVTTL LVTTL LVTTL LVTTL 3-state 3.3 V 3 mA 3.3 V 3 mA 3.3 V 3 mA 3.3 V 3 mA Nonstandard signal detection monitor output ('L' : standard, 'H' : nonstandard) EXADINS=0: Digital YC signal alternate output EXADINS=1: Digital video data input for external ADC (Pull down unuse lower bit pins via resistor) DYCO0 is the LSB, DYCO9 is the MSB. 73 ALTF O LVTTL 3.3 V 3 mA EXADINS=0: Digital YC signal alternate flag output ('L' : C, 'H' : Y) EXADINS=1: 4fSC clock output for external ADC 74 76 77 86 87 88 89 90 91 92 93 94 95 96 97 98 LINE KIL CSI AVDD CBPC ACO AYO CBPY AGND AGND AYI VCLY VRBY VRTY VCOMY AVDD I I I O O O O I O O O O LVTTL LVTTL Schmitt Analog Analog Analog Analog Analog Analog Analog Analog Analog 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 3.3 V PD:50 3.3 V PD:50 3.3 V PU:50 Y-DAC and C-DAC 2.5 V supply voltage C-DAC phase compensation output C-DAC analog C signal output Y-DAC analog Y signal output Y-DAC phase compensation output Y-DAC and C-DAC ground ADC ground ADC analog composite signal input ADC clamp potential output ADC bottom reference voltage output ADC top reference voltage output ADC common mode reference voltage ADC 2.5 V supply voltage Forced inter-line processing selection input ('L' : ordinary processing, 'H' : forced inter-line processing) External killer input ('L' : ordinary processing, 'H' : forced Y/C separation stop) Composite sync input (Active-low) Internal signal monitor output 1 Description
57
CLK8
I/O
LVTTL 3-state
CKMD = 0 : 8fSC clock output CKMD = 1 : 8fsc clock input System reset input (Active-low) (Active-low reset pulse is input from the outside.) Internal signal monitor output 0
58
RSTB
I
Schmitt
10
Data Sheet S16021EJ2V0DS
PD64084
2. SYSTEM OVERVIEW 2.1 Operation Modes
The PD64084 can operate in the following major four signal processing modes. Mode selection is performed according to NRMD on the serial bus. Table 2-1. Operation Modes
Serial bus setting Mode name NRMD = 0 YCS mode Y/C separation AYI : Composite signal Burst locked clock (4fSC, 8fSC) * For standard signals, motion-adaptive threedimensional Y/C separation is performed. * For nonstandard signals, inter-line Y/C separation is performed.
Comp. ADC 4fSC YCS (3D/2D) DAC DAC Y C
Function Note
Pin input
System clock
Feature Model diagram
4-Mbit memory
NRMD = 1 YCS+ mode
2D Y/C separation and YCNR
AYI : Composite signal
Burst locked clock (4fSC, 8fSC)
* Inter-line Y/C separation and Frame recursive YNR and CNR is performed.
Comp. ADC 4fSC YCS (2D) YNR CNR 4-Mbit memory DAC DAC Y C
Note
3D Y/C separation, Frame-recursive YNR/CNR, each function is independence. So these don't operate at the same time.
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Data Sheet S16021EJ2V0DS
PD64084
2.2 Filter Processing
Table 2-2 lists filters used in each mode. Table 2-2. Filter Matrix
Mode Standard / nonstandard / killer signal detection Effective-picture period Still picture portion YCS mode (NRMD = 0) Nonstandard signal detected Killer signal detected YCS+ mode (NRMD = 1) Standard or horizontal nonstandard signal detected Vertical nonstandard signal detected Killer signal detected Vertical contour compensation / Y peaking Y output: Through (Y/C separation stop) C output: Separated C signal Active Through Line comb Band-pass Note Line comb Y output: Through (Y/C separation stop) C output: Separated C signal Line comb + Frame recursive Line comb Band-pass Note Band-pass Note Standard signal detected Frame comb Moving picture portion Filter selected Blanking period Horizontal (11 s) Vertical (1H to 22H) Band-pass Note
Line comb
Note Setting serial bus register SA09h: D0 (VFLTH) enables through output.
2.3
System Delay
The following diagram shows a model of system delays (video signal delays). Figure 2-1. System Delay Model
DYCO9-2 Composite Input AYI 1 ADC 10 0 1H Delay 910 YCS/YNR 21 CNR/Delay 21 Filter 4 Delay 0~7 Y Outpur AYO C Output ACO
Y-DAC 1 C-DAC 1
SA02h:D5 EXADINS C Sync. Input CSI
Timing Gen.
CDL SA03h:D2-D0
Remark 1 corresponds to a one-clock pulse delay (4fSC or 910 fH = about 69.8 ns).
12
Data Sheet S16021EJ2V0DS
PD64084
2.4 Start-up of Power Supply and Reset
It is necessary to reset the I2C bus interface immediately when it is supplied with power. When reset, the I2C bus interface releases its SDA line and becomes operative. In addition, its write register is previously loaded with an initial value. <1> When the power is switched on, wait until the power supply line reaches and settles on a 3.3-V/2.5-V level before starting initialization. <2> Initialize the I2C bus interface circuit by keeping the RSTB pin at a low level for at least 10 s. <3> Start communication on the I2C bus interface after 100 s from pull up the RSTB pin to a high level. Figure 2-2. I2C Bus Interface Reset Sequence
Power ON
RSTB='L' RSTB='H' 3.3 V start-up 3.3 V cut-off
3.3 V
DVDDIO
0V
2.5 V start-up
2.5 V
2.5 V cut-off
DVDD
0V
3.3 V
RSTB
0V
10 s MIN. Don't care I2C bus access disable
100 s MIN.
I2C bus access enable Serial bus register data setting
Caution
Reset is always necessary whether using the serial bus register or not.
13
Data Sheet S16021EJ2V0DS
PD64084
3. VIDEO SIGNAL INPUT BLOCK
This block converts analog video signals to digital form. Figure 3-1. Video Signal Input Block Diagram
PC659A
Composite input (When the external ADC used) VIN DB1-DB8 VRT 47 k VCL 15 k VRB Composite input (When the internal ADC used) 140 IRE = 0.8 Vp-p 10 to 47 F 0.1 F 0.1 F 0.1 F 0.1 F Analog section supply voltage 2.5 V 0.1 F CLK PCL 4fSC,910fH 1F ST0 ALTF AGND AYI Clamp VCLY VRBY VRTY VCOMY AVDD CLK 4fSC 10-bit ADC (10) 10 1 0 EXADINS
Sampling clock Clamp level feedback
100 x8 100 x2
DYCO9-2 DYCO1-0
8 2
10
ST0S=01
Clamp pulse generator
Pedestal level error detection 256 10 Internal
3.1
Video Signal Inputs
The composite signal is input to the AYI pin. This analog video (composite) signal converts to digital video signal at internal 10-bit ADC (EXADINS = 0). In case of external ADC used, 10-bit composite signals in digital form are input to the DYCO9 to DYCO0 pins (EXADINS = 1).
3.2
Pedestal Level Reproduction
This circuit reproduces the pedestal level of a video signal. The pedestal level error detection circuit detects the difference between that level and the internal fixed value of 256 LSB levels, and outputs the feedback level. This output signal is connected to VCLY pin via internal resistor to feed back to video signal for fixing pedestal level to 256 LSB. Pull down the VCLY pin via a 0.1 F bypass capacitor and a 10 to 47 F electrolysis capacitor for loop filter. Caution In case of H-Sync input level is bigger than 256LSB, this pedestal level also becomes over 256LSB. Do not use this circuit when the external ADC is used.
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Data Sheet S16021EJ2V0DS
PD64084
3.3 Video Signal Input Level
It is necessary to limit the level of video (composite) signal inputs to within a certain range to cope with the maximum amplitude of the video signal and variations in it. Figure 3-2 shows the waveform of the video signal input whose amplitude is 140 IREp-p = 820 LSB (0.8 times a maximum input range of 1024 LSB). In this case, it is possible to input a white level of up to 131 IRE for the Y signal and up to 175 IREp-p for the C signal. Figure 3-2. Video Signal Input Waveform Example (for 75% Color Bar Input)
AYI pin input +131 IRE
1.6 V MAX. 131 IRE = 1023 LSB
1023 896 100 IRE = 840 LSB
140 IREp-p = 0.8 x 1024 LSB = 820 LSB
768 640 512 384 256 Pedestal: 0 IRE = 256 LSB Sync-tip: -40 IRE = 20 LSB 128 0
0 IRE
-43 IRE
0.6 V
Remark The recommended input level of video signals is 140 IREp-p = 0.8 Vp-p (1.00 V x 0.8).
3.4
* *
Pin Treatment
Supply 2.5 V to the AVDD pins. Isolate them sufficiently from the digital section power supply. Use as wide wiring patterns as possible for the ground lines of each bypass capacitor and the AGND pins so as to minimize their impedance.
*
Connect a video signal to the AYI pin by capacitive coupling. Maintain low input impedance for video signals. Be sure to keep the wiring between the capacitor and the AYI pin as short as possible. Pull down the VRTY, VRBY and VCOMY reference voltage pins via a 0.1 F bypass capacitor. Pull down the VCLY pin via a 0.1 F bypass capacitor and a 10 to 47 F electrolysis capacitor. Do not bring the digital system wiring (especially the memory system) close to this block and the straight downward of the IC.
* * *
DYCO9-0 Input / Digital level (LSB)
1.00 Vp-p
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Data Sheet S16021EJ2V0DS
PD64084
3.5 External ADC Connection Method
Setting up EXADINS = 1 on the serial bus puts the IC in the external ADC mode. In this mode, the ALTF pin is used to output 4fSC sampling clock pulses, and the DYCO9 to DYCO0 pins are used to receive digital data inputs. Setting up ST0S = 01 on the serial bus causes a clamp pulse to be output from the ST0 pin. It is used as a pedestal clamp pulse for external ADC. The clamp potential for the pedestal level of external ADC must be determined so that the sampled value becomes about 256 8LSB. Supply converted 10-bit data to the DYCO9 to DYCO0 pins via a 100 resistor. For using 8-bit ADC (exp. PC659A), Pull down the DYCO1 and DYCO0 pins via 100 resistor. In this mode, for ADC in the PD64084, keep the VRTY, VRBY and VCOMY pins open, and pull down the VCLY and AYI pins via a 0.1 F capacitor. Figure 3-3. Example of Application Circuit Set Up for External ADC
5V 0.1 F 47 k: 1% 10 F 0.1 F Composite input Clamp Bias 0.1 F 2.2 F 15 k: 1% 0.1 F 1F
140 IRE = 0.8 Vp-p
VRT (Pin 1) CLK OVER NC MSB: DB1 AVCC VIN DB2 AGND DB3 DGND PCL DVCC VCL AVCC DB4 AGND DB5 DB6 VRB AVCC DB7 AGND LSB: DB8 PC659AGS Clamp pulse
10
4fSC 100 x10
ALTF (Pin 73) DYCO9 (Pin 72): MSB DYCO8 (Pin 71) DYCO7 (Pin 70)
0.1 F 10 F
DYCO6 (Pin 69) DYCO5 (Pin 68) DYCO4 (Pin 67) DYCO3 (Pin 66) DYCO2 (Pin 65): LSB DYCO1 (Pin 64) DYCO0 (Pin 63) ST0 (Pin 59)
Remark Serial bus registers setting: EXADINS = 1, ST0S = 01
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Data Sheet S16021EJ2V0DS
PD64084
4. CLOCK/TIMING GENERATION BLOCK
This block generates system clock pulses and timing signals from video signals. Figure 4-1. Clock/Timing Generation Block Diagram
System clock (8fSC, 1820fH) System clock (4fSC, 910fH)
1/2
CLK8 AVDD 8fSC PLL FSCI AGND
2.5 V power supply voltage 10 F 0.1 F 0.01 F
Composite sync signal
System timing CSI Timing generator
Y/C separation stop, CNR stop DAC
AGND FSCO AVDD
fSC BPF
Sync. separator
0.1 F 0.1 F 22 to 33 pF 20 MHz,16 pF 22 to 33 pF
Composite input
AYI
ADC
Sync. separator
Horizontal phase detection
Killer detection PLL filter
fSC generator
DVDD XO XI DGND
Burst phase detection
4.1
Sync Separator and Timing Generator
These sections separate horizontal and vertical sync signals from the composite signal sampled at 4fSC or 910fH, and generate system timing signals by using them as references.
4.2
Composite Sync Signal Input
An active-low composite sync signal separated from the video signal is input at the CSI pin. This input is used as a reference signal to lock onto sync at the timing generator.
4.3
Horizontal/Burst Phase Detection Circuit
The horizontal phase detection circuit extracts the horizontal sync signal from the Y signal sampled at 4fSC or 910fH to detect a horizontal phase error. This phase error is used for generation of 227.5fH and timing generator. The burst phase detection circuit extracts the burst signal from the composite signal sampled at 4fSC to detect a burst phase error. This phase error is used for fSC generation.
4.4
PLL Filter Circuit
The PLL filter circuit integrates a burst or horizontal phase error to determine the oscillation frequency of the fSC generator ahead.
4.5
Killer Detection Circuit
The killer detection circuit compares the amplitude of the burst signal with the KILR value set on the serial bus to judge on a color killer. If the burst amplitude becomes smaller than or equal to the set KILR value when the burst locked clock is operating, the fSC generator is allowed to free-run.
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Data Sheet S16021EJ2V0DS
PD64084
4.6 fSC Generator
The fSC generator generates fSC (or 227.5fH when the line locked clock is running) from an oscillation frequency determined in the PLL filter. fSC is converted by internal DAC to an analog sine waveform before it is output from the FSCO pin. Because this output contains harmonic components, they must be removed using an external band-pass filter (BPF) connected via a buffer, before the analog sine waveform is input to the FSCI pin via a capacitor. The fSC generator uses a 20 MHz free-run clock pulse as a reference.
4.7
8fSC-PLL Circuit
The 8fSC-PLL circuit generates 8fSC (or 1820fH) from fSC (or 227.5fH) input at the FSCI pin. The 8fSC signal is output from the CLK8 pin. It is also used as the internal system clock.
4.8
* *
Pin Treatment
Supply 2.5 V to the AVDD pins. Isolate them sufficiently from the digital section power supply. Use as wide wiring patterns as possible for the ground lines of each bypass capacitor and the DGND and AGND pins so as to minimize their impedance.
*
Connect a 20-MHz Crystal resonator across the XI and XO pins. Provide guard areas using ground patterns to keep these pins from interfering with other blocks. Table 4-1 shows the crystal resonator specification example. Connect a BPF to the FSCO pin via an emitter follower. Supply the fSC signal to the FSCI pin via a capacitor. Pull down the RPLL pin via a 0 resistor. Input an active-low composite sync signal to the CSI pin. Figure 4-2 shows the external composite sync separator application circuit example. Table 4-1. Crystal Resonator Specification Example
Parameter Frequency Load Capacitance Equivalent Serial Resistance Frequency Permitted Tolerance Frequency Temperature Tolerance Specification 20.000000 MHz 16 pF 40 or less 50 ppm or less 50 ppm or less
* * *
Figure 4-2. External Composite Sync Separator Application Circuit Example
Power Supply (3.3 V) 1F Composite Signal (1 Vp-p)
0.1 F 220 1000 pF to 2200 pF
22 k
1 k
4.7 k Composite Sync. Output
220 k
2.2 k
470
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Data Sheet S16021EJ2V0DS
PD64084
5. COMB FILTER BLOCK
This block performs Y/C separation or frame comb type YNR according to the result of checks in various detection circuits. Figure 5-1. Comb Filter Block Diagram
Composite input 0H H 1H H 2H Frame Memory H 526H H
Frame comb filter
Delay Mixer circuit Line comb filter C2
L H
YOUT 0
Y signal output
k
COUT
C signal output
Delay Motion detection
Nonstandard signal detection
C3
1-k
k =1 k
H L
H: Nonstandard signal detected H: Killer signal detected
LINE KIL
Killer detection
5.1
Line Comb Filter
The C signal is separated from video signals that have been delayed by 0H, 1H, and 2H. This filter serves as a logical comb filter based on inter-line correlation to reduce dot and cross-color interference. The filter output (C2) is used in the moving picture portion of standard signals, nonstandard signals, and blanking periods.
5.2
Frame Comb Filter
The C signal is separated from video signals that have been delayed by 1H and 526H. The filter output (C3) is used in still picture portions by the motion detection circuit.
5.3
Mixer Circuit
The mixer circuit mixes C signals to adapt to the motion according to the motion factor from the motion detection circuit. In other words, COUT is generated by mixing the line comb filter output (C2) and the frame comb filter output (C3) by a mixture ratio according to the motion factor k (0 to 1). If the input signal is a nonstandard signal, or if the LINE pin is at a high level, C2 is output without performing motion-adaptive mixture.
5.4
1H.
C Signal Subtraction
Subtraction is quitted when the killer detection circuit detects that the input signal is a color killer signal
The YOUT signal is separated by subtracting the COUT signal from a composite video signal that has been delayed by (monochrome signal or non-burst signal) or that the KIL pin is at an 'H' level.
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Data Sheet S16021EJ2V0DS
PD64084
6. MOTION DETECTION BLOCK
This block generates a 4-bit motion factor indicating an inter-frame motion level from the video signal inter-frame difference. This motion factor is used as a mixture ratio to indicate how the frame and line comb filter outputs are mixed. This block is used in the YCS mode. Figure 6-1. Motion Detection Block Diagram
Composite input Y1 H Frame memory H Line comb filter H (previous frame) Line comb filter H (current frame) Y2 C1 C2
DY detection circuit
DYCOR DYGAIN DY
Coring Gain LIM Maximum value section Gain LIM
To the mixer circuit MD[3:0] 0
Expansion circuit
LPF
|x|
F 0 0 MSS1
4 MSS0
|x| |x|
DC detection circuit
LPF
|x|
DC
Coring
Motion factor generation circuit
DCCOR DCGAIN
6.1
Line Comb Filter
Before obtaining an inter-frame difference, the line comb filter performs Y/C separation for the composite signals of both frames.
6.2
DY Detection Circuit
The DY detection circuit detects a Y signal inter-frame difference. After a Y signal difference between the current and previous frames is obtained, its absolute value, obtained by limiting the frequency band for the Y signal difference using an LPF, is output as a Y frame difference signal, or a DY signal.
6.3
DC Detection Circuit
The DC detection circuit detects a C signal inter-frame difference. After a C signal difference between the current and previous frames is obtained, its absolute value, obtained by limiting the frequency band for the C signal difference using an LPF, is output as a C frame difference signal, or a DC signal. Because the phase of the C signal is inverted between frames, the absolute values of the C signals of both frames have been obtained before the difference is obtained.
6.4
Motion Factor Generation Circuit
The motion factor generation circuit generates a 4-bit motion factor from the DY and DC signals. The first coring circuit performs coring according to the DYCOR and DCCOR settings on the serial bus to block weak signals like noise. The gain adjustment circuits ahead perform gain adjustment according to the DYGAIN and DCGAIN settings on the serial bus to specify the sensitivity of the motion factor. These outputs are limited to a 4-bit width, and one having a higher level is selected for output by the maximum value selection circuit. The selected signal is expanded horizontally, then output as a final motion factor.
6.5
Forcible Control for The Motion Factor
The motion factor can be set to 0 (forced stop) or a maximum value (forced motion) using the MSS signal on the serial bus.
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Data Sheet S16021EJ2V0DS
PD64084
7. YNR/CNR BLOCK
This block performs frame recursive YNR and CNR. It is used in the YCS+ mode. Figure 7-1. YNR/CNR Block Diagram
Y signal input C signal input
H H
Current Y Current C
Frame difference
Delay Delay YNR nonlinear filter CNR nonlinear filter
Noise component
Y signal output Substraction of noise component Modulation Y' C signal output
Demodulation
1H+ 526H 1H+ 526H Frame Memory
Y
Previous frame Y
Frame difference
Noise component
C
C'
Previous frame C
YNRK CNRK YNRINV CNRINV YNRLIM CNRLIM
Nonstandard signal detection YNR/CNR stop signal Killer signal detected
LINE KIL
Killer detection
7.1
YNR/CNR Processing
The frame difference (Y) signal is generated by subtracting the previous frame Y signal from the current frame Y signal. The noise component Y' signal is extracted by eliminating the motion component of the Y signal at the nonlinear filter. Noise components are reduced by subtracting the noise component Y' signal from the current frame Y signal. At the same time, the Y signal submitted to noise reduction is delayed by a frame to be used to generate Y for the next frame. This way the frame recursive YNR is configured. Much the same processing is performed for the C signal to reduce noise components.
7.2
Nonlinear Filter
Y and C contain inter-frame motion
The Y' and C' noise components are extracted from Y and C.
components and noise components. Subtracting Y and C from the current frame Y and C signals causes inter-frame motion components to remain in the output picture. To solve this problem, a nonlinear filter that passes only lowamplitude signals is used; generally, motion components have a large amplitude, while noise components have a small amplitude. How nonlinear the filter is to be is specified using YNRK, YNRLIM, YNRINV, CNRK, CNRLIM, and CNRINV on the serial bus.
7.3
YNR/CNR Operation Stop
If the nonstandard signal detection circuit detects a vertical nonstandard signal or frame sync nonstandard signal, or the LINE pin is at a high level, the killer detection circuit detects a color killer signal, or the KIL pin is at a high level, YNR and CNR operations are stopped.
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Data Sheet S16021EJ2V0DS
PD64084
8. NONSTANDARD SIGNAL DETECTION BLOCK
This block detects nonstandard signals not conforming to the NTSC standard, such as VCR playback signals, home TV game signals, and Laser-Disc special playback signals. The detection result is used to stop inter-frame video processing. (and selects intra-field video processing forcibly.) Figure 8-1. Nonstandard Signal Detection Block Diagram
fSC trap Video signal input Coring WSS WSC
Sync separation
Noise level detection
Frame sync nonstandard signal detection Vertical sync nonstandard signal detection
Inter-frame processing control Signal to stop using YNR, CNR, and frame comb filter H: Nonstandard Forced standard or signal detected nonstandard signal control
WSL
HV counter
NSDS Mixer LDSDF OVSDF Read register OHSDF
LINE NSTD
LDSR VTRH VTRR
Horizontal sync nonstandard signal detection
8.1
Horizontal Sync Nonstandard Signal Detection
The horizontal sync nonstandard signal detection circuit detects signals not having a standard relationship between fSC and fH (fSC = 227.5fH) like a VCR playback signal. The sensitivity of detection is set using VTRR and VTRH on the serial bus. If the circuit detects a nonstandard signal, it stops using the frame comb filter. The detection result can be read using OHSDF on the serial bus.
8.2
Vertical Sync Nonstandard Signal Detection
The vertical sync nonstandard signal detection circuit detects signals not having a standard relationship between fH and fV (fH = 262.5fV) like a VCR special playback signal and home TV game signal. The sensitivity of detection cannot be set. If the circuit detects a nonstandard signal, it stops using the frame comb filter, YNR, and CNR. The detection result can be read using OVSDF on the serial bus.
8.3
Frame Sync Nonstandard Signal Detection
The frame sync nonstandard signal detection circuit detects signals out of horizontal sync phase between frames, such as a laser-disc special playback signal. The sensitivity of detection is set using LDSR on the serial bus. If the circuit detects a nonstandard signal, it stops using the frame comb filter, YNR, and CNR. The detection result can be read using LDSDF on the serial bus.
8.4
Forced Standard or Nonstandard Signal Control
It is possible to specify either forced standard or nonstandard signal control using NSDS on the serial bus.
8.5
Noise Level Detection
The noise level detection circuit detects a noise level in the flat portion of a video signal. The sensitivity of detection is set using WSCOR on the serial bus. The detection result can be read using WSL on the serial bus; it is not used in the IC. The detection result can be processed in a microprocessor to find a weak electric field.
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Data Sheet S16021EJ2V0DS
PD64084
9. WCV-ID DECODER / ID-1 DECODER BLOCK
This block decodes ID-1 signal of 20H/283H and an identification control signal superimposed on a wide clear vision signal of 22H and 285H (The wide clear vision standard applies only in Japan).
9.1
WCV-ID Decoder
The WCV-ID decoder checks whether the video signal contains an ID signal by examining mainly the following seven items. If all these items turn out to be normal, an ID signal is detected. The check and decode results are output to the ED2 bit and bits B3 to B17 on the serial bus, respectively. In addition, the phase of the confirmation signal is detected. <1> A difference in DC level between B1 and B2 is not smaller than a certain value. <2> The DC level of the SCH part is not higher than a certain value. <3> The fSC amplitude of the NRZ part is not larger than a certain value. <4> The fSC amplitude of the SCH part is not smaller than a certain value (if FSCOFF = 0), <5> Items <1> to <4> continue for at least 12 fields. <6> The parity of the NRZ part (B3 to B5) is normal.
Note Note
<7> The CRC of the NRZ part and SCH part (B3 to B23) is normal.
Note If an error is detected in item <6> or <7>, bits B3 to B17 on the serial bus hold the decoded value for the previous field.
Figure 9-1. Wide Clear Vision ID Signal Configuration
ED2 bit (0: No ID signal, 1: ID signal) SA02
MSB LSB
SA03
MSB
LSB
Color burst
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27
10 0 NRZ part SCH part CRC code Confirmation signal
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Data Sheet S16021EJ2V0DS
PD64084
9.2 ID-1 Decoder
The ID-1 decoder checks whether the video signal contains an ID-1 signal by examining mainly the following five items. If all these items turn out to be normal, an ID signal is detected. <1> A difference of DC level between Ref signal and the pedestal level is not smaller than a certain value. <2> The width of each bit is not smaller than a certain value. <3> Items <1> to <2> continue for at least 6 fields. (When FELCHK register is set to zero, this check is disable) <4> CRC check is passed. Remark If any errors are detected in item <1> to <3>, the output for serial bus hold the decoded value for the previous field. If item <3> is disabled by setting FELCHK register to zero, CRC check is also disabled. If any errors are detected by CRC check, the output for serial bus will be initialized. Initial values of serial bus registers are WORD0 = 00, WORD1 = 1111, WORD2 = 00h.
Figure 9-2. ID-1 Signal Configuration
SA04 SA05
MSB
LSB
MSB
LSB
Color burst
10 WORD0 WORD1 WORD2 CRC code
24
Data Sheet S16021EJ2V0DS
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20
Ref
PD64084
10. Y SIGNAL OUTPUT PROCESSING BLOCK
After Y/C separation or Y Noise reduction, this block performs high-frequency coring, peaking, and vertical aperture compensation for the Y signal submitted to YNR processing. Figure 10-1. Y Signal Output Processing Block Diagram
ID1ENW0A1 ID1ENW0A2
ID-1 encoder
Y low-frequency 1 0 0 1 0
Composite input
Line comb filter
Y/C separation Y HH decoding YNR
HPF Y highfrequency
Coring
20/283H ID1ON
1
YAPS1 Y signal output (to the DTCO pin) YAPS0 Y signal output (to the Y-DAC pin)
YHCOR Y high-frequency coring circuit
BPF Coring
YHCGAIN Peaking component + vertical aperture conpensation component
k
YPFT
2
YPFG
Y peaking filter circuit
LPF Coring Limiter
Vertical high-frequency component 1
k
VAPGAIN
VAPINV
Vertical aperture compensation circuit
10.1 Y High-Frequency Coring Circuit
The Y high-frequency coring circuit performs coring for the high-frequency component of the Y main line signal. It works as a simplified noise reducer, because it can eliminate high-frequency components at 1 LSB to 3 LSB levels. The coring level is set using YHCOR on the serial bus. <1> HPF circuit : Separates the input Y signal into the low- and high-frequency components. outputs a Y signal by adding the Y high- and low-frequency components after they are submitted to coring. The coring effect can set 1/2 times by the YHCGAIN setting.
<2> Coring circuit : Performs coring for Y high-frequency components according to the YHCOR setting, and
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Data Sheet S16021EJ2V0DS
PD64084
10.2 Y Peaking Filter Circuit
The Y peaking filter circuit performs peaking processing for the Y signal to correct the frequency response of the Y signal. <1> BPF circuit : Extracts high-frequency components from the original Y signal according to the YPFT setting on the serial bus. The center frequency of the BPF can be selected from 3.58, 3.86, 4.08, and 4.22 MHz. <2> Coring circuit : Performs 2LSB (in 8-bit terms) coring for Y high-frequency components to prevent S/N deterioration during peaking processing. <3> Gain adjustment circuit : Performs gain adjustment for peaking components according to the YPFG setting on the serial bus. The gain to be added can be changed in 16 steps over a range between -1.000 times and +0.875 times. <4> Addition to the main line : Y peaking components, together with vertical aperture compensation components, are added to the Y signal.
10.3 Vertical Aperture Compensation Circuit
The vertical aperture compensation circuit extracts vertical contour components from a Y signal and adds them to the Y signal to emphasize contours. <1> Line comb filter <2> LPF circuit <3> Coring circuit : Extracts vertical high-frequency components from the video signal. : Eliminates C signal components and Y signal slant components to extract vertical contour components. : Performs 1LSB (in 8-bit terms) coring for vertical high-frequency components to prevent S/N deterioration during aperture compensation. <4> Gain adjustment circuit : Performs gain adjustment for aperture compensation components according to the VAPGAIN setting on the serial bus. <5> Limiter circuit (nonlinear processing) : Performs limit processing for aperture compensation components according to the VAPINV setting on the serial bus. Signals for which contours are to be emphasized are rather weak ones. Uniform emphasis would result in initially large signals becoming too large. To solve this problem, the limiter circuit blocks signals larger than the VAPINV setting, thereby disabling contour emphasis for large signals. <6> Addition to the main line : Vertical aperture compensation components, together with Y peaking components, are added to the Y signal.
10.4 Turning On/Off Y Peaking and Vertical Aperture Compensation
The YAPS setting on the serial bus can be used to turn Y peaking and vertical aperture compensation on and off.
10.5 ID-1 Encoder
Bit information conforming to the ID-1 standard (CPX-1204) can be superimposed on the Y signal output at 20H/283H. ID1ENON on the serial bus specifies whether to turn on or off superimposition. ID1ENW0A1 and ID1ENW0A2 specify the bit information to be superimposed. If ID-1 information has already be superimposed on the original signal, it will be replaced with the newly specified ID-1 information.
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Data Sheet S16021EJ2V0DS
PD64084
11. C SIGNAL OUTPUT PROCESSING BLOCK
After Y/C separation, the C signal output processing block performs delay adjustment, BPF processing, and gain adjustment for the C signal submitted to CNR processing. Figure 11-1. C Signal Output Processing Block Diagram
BPF (fSC) x2 COUTS0
C signal input
Variable delay (0~7)
C signal output
CDL
COUTS1
11.1 C Signal Delay Adjustment
The delay time of the C signal can be varied in a range between 0 and 7 clock pulses (4fSC) according to CDL on the serial bus. This way, the delay of the C signal relative to the Y signal can be set to anywhere between -4 clock pulses (-280 ns) and +3 clock pulses (+210 ns).
11.2 BPF and Gain Processing
COUTS on the serial bus can be used to specify whether to insert a BPF. It can also be used to specify the gain (x2 or x1).
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Data Sheet S16021EJ2V0DS
PD64084
12. VIDEO SIGNAL OUTPUT BLOCK
The video signal output block can convert digital video signals to analog form. It can also output digital video signals without performing D/A conversion. Figure 12-1. Video Signal Output Block Diagram
Digital YC / alternate flag output
DYCO
ALTF
Supply voltage 2.5 V for analog block 10 F AVDD CBPY 10 2ch 10-bit DAC (Z-1) AYO ACO CBPC CLK AGND 0.1 F Analog C output 0.1 F 0.1 F Supply voltage Analog Y output
DYCOS1 4fSC,910fH Y signal input
Y signal output processing
C signal input C signal output
processing
10
System clock (4fSC)
12.1 Digital YC Output Processing
When setting up DYCOS = 00 on the serial bus, DYCO9 (MSB) to DYCO0 (LSB) pins alternately output 10 bits of Y signals in straight binary and 10 bits of C signals in offset binary. And ALTF pin outputs alternative flag of Y or C signals. When ALTF = 'L' means "C Signal Outputs", when ALTF = 'H' means "Y Signal Outputs". When setting up DYCOS = 1x on the serial bus, DYCO9 (MSB) to DYCO0 (LSB) and ALTF pins are high-impedance. When the DYCO pins are not used, setting DYCOS = 1x on the serial bus reduces radiation noise of these pins. When the external ADC is used, DYCO9 to DYCO0 pins are used as the digital input terminal of video signal. So the digital YC output is not available.
12.2 Video Signal Output Level
Figure 12-2 shows sample waveforms that would be observed at the AYO and ACO pins after a typical video signal is input (see 3. VIDEO SIGNAL INPUT BLOCK).
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Data Sheet S16021EJ2V0DS
PD64084
Figure 12-2. Video Signal Output Waveform Example (for 75 % Color Bar Input)
+131 IRE: 1023 MAX. 131 IRE = 1023 LSB 896 100 IRE = 840 LSB
IRE: DYCO output (LSB)
1.94 V
768
140 IREp-p = 0.8 Vp-p = 820 LSB
640 512 384 0 IRE: 256 128 -43 IRE: 0
Pedestal: 0 IRE = 256 LSB Sync-tip: -40 IRE = 20 LSB
0.94 V
+87 IRE: 1023 896 768 640 0 IRE: 512 384 256 128 -87 IRE: 0
1.94 V COUTS = 0x COUTS = 1x
Burst: 40 IREp-p = 0.23 Vp-p = 234 LSB MAX.: 175 IREp-p = 1 Vp-p = 1023 LSB
IRE: DYCO output (LSB)
Center = 512 LSB 0.94 V
12.3 Pin Treatment
*
Supply 2.5 V to the AVDD pins and supply 3.3 V to the DVDDIO pin. Isolate them sufficiently from the digital section power supply. Use as wide wiring patterns as possible as the ground lines of each bypass capacitor and the AGND pins so as to minimize their impedance. Pull down the CBPY and CBPC pins via a 0.1 F bypass capacitor. When DAC aren't used, connect AGND pin to digital ground, AVDD pin to digital power supply, and AYO, ACO, CBPY and CBPC pins set open. When the digital I/O pin DYCO9 to DYCO0 aren't used, these pins set open.
*
* *
*
ACO output (V, TYP.)
AYO output (V, TYP.)
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Data Sheet S16021EJ2V0DS
PD64084
13. EXTEND DIGITAL INPUT / OUTPUT
This device have the extend digital I/O terminals EXTDYCO9-EXTDYCO0 in addition to DYCO9-DYCO0. Using these terminals, the digital in to digital out system is available.
Table 13-1. Mode setting for extend digital I/O terminals
Serial bus EXTDYCO 0 0 0 1 1 1 1 EXADINS 0 1 0 0 1 0 1 DYCOS[1] 0 x 1 0 0 1 1 DYCOn OUT IN Low Note OUT OUT Low Note IN EXTD YCOn Low Low
Note Note
Condition of each terminals ALTF FLAG 4fsc Low FLAG FLAG Low 4fsc EXTALTF Low Low Low Low 4fsc FLAG FLAG A/D ON OFF ON ON OFF ON OFF D/A ON ON ON ON ON ON ON
Low Note Low
Note
IN OUT OUT
Note By setting HIZEN (SA16h, D4) = 1, these pin status are set to Hi-Z.
13.1 Usage of extend digital I/O terminals
The extended digital I/O pin EXTDYCO9 to EXTDYCO0 becomes effective by setting serial bus to EXTDYCO = 1. At this time, internal ADC can not be available. The I/O mode selection of EXTDYCO9 to EXTDYCO0 are set by serial bus DYCOS. When using input mode of DYCOn or EXTDYCOn pins, insert serial resistor in the lines.
13.2 Digital YC output format
The specification of the digital input and output for the extended digital I/O pin EXTDYCO9 to EXTDYCO0 is same as usual digital I/O pin DYCO9 to DYCO0. When using in input mode, input 10-bit digitized composite video signal that is sampled by 4fsc. And when using in output mode, EXTDYCO9 (MSB) to EXTDYCO0 (LSB) pins alternately output 10 bits of Y signals in straight binary and 10 bits of C signals in offset binary. And EXTALTF pin outputs alternative flag of Y or C signals. When ALTF = 'L' means "C Signal Outputs", when ALTF = 'H' means "Y Signal Outputs". The internal ADC and extended digital I/O can't work at the same time. And extended digital I/O pins have 3.3 V resistant.
13.3 Pin Treatment
*
When the extended digital I/O pin EXTDYCO9 to EXTDYCO0 aren't used, these pins set open.
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Data Sheet S16021EJ2V0DS
PD64084
14. DIGITAL CONNECTION WITH GHOST REDUCER IC PD64031A
The PD64084 can perform processing from ghost reduction to three-dimension Y/C separation digitally in 10-bit units when it is directly connected to NEC Electronics' ghost reducer IC PD64031A. Figure 14-1 shows the system configuration when the PD64031A and PD64084 are digitally connected directly.
14.1 Outline
When signals are input from a ground wave tuner, the composite video signal is first input to the A/D converter of the PD64031A, where the ghost of the signal is reduced. The digital clamp circuit then adjusts the pedestal level, and the digital amplifier circuit adjusts the amplitude of the signal. As a result, a 10-bit digital composite video signal is sent to the three-dimension Y/C separation IC PD64084. The PD64084 then performs processing such as Y/C separation and outputs a Y/C video signal that has been converted into an analog signal (see Figure 14-1). Figure 14-1. Example of Digital Connection System with Ghost Reducer (when signals are input from tuner)
Tuner input Composite video signal input
Y/C video output C sync separation
ADC
10-bit digital composite video signal Digital clamp amplifier
DO9 to DO0 ALTF OCP Delay
8fSC system clock
ADC
DAC
DAC
GR filter
DYCO9 to DYCO0 ALTF ST0 CSI
Chroma, sync signal
Y/C separation
4fSC
Clamp pulse
1/2
CSO WP1 CLK8 CKMD CLK8 input and 8fSC PLL stop
8fSC system clock
Chroma signal
ACO
AYO
VIN
CSI
AYI
Burst flag
Burst flag
CLK8 CKMD
fSC generator
8fSC PLL
fSC/227.5fH generator
8fSC PLL
FSCO
FSCO
C20O
FSCI
fSC BPF 8fSC fSC 20 MHz fSC path selection
PD64031A
PD64084
FSCI
XO
XO
XI
XI
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Data Sheet S16021EJ2V0DS
PD64084
When signals are input from video (composite or S input), the PD64031A is not used, and the video signal is directly input to the A/D converter of the PD64084 (see Figure 14-2). Figure 14-2. Example of Digital Connection System without Ghost Reducer (when signals are input from external source)
External pin input, etc. Composite video signal input
Y/C video output C sync separation
ADC Digital clamp amplifier
10-bit digital composite video signal DO9 to DO0 ALTF OCP DYCO9 to DYCO0 ALTF ST0 CSI
Chroma, sync signal
ADC
DAC
DAC
GR filter
Y/C separation 4fSC Clamp pulse 1/2
Delay
8fSC system clock
CSO WP1 CLK8 CKMD CLK8 input and 8fSC PLL stop
8fSC system clock
Chroma signal
Burst clamp
Burst clamp
ACO
AYO
VIN
CSI
AYI
CLK8 CKMD
fSC generator
8fSC PLL
fSC/227.5fH generator
8fSC PLL
FSCO
FSCO
C20O
FSCI
8fSC fSC 20 MHz
fSC BPF
3DYC/GR selection
PD64031A
PD64084
32
Data Sheet S16021EJ2V0DS
FSCI
XO
XO
XI
XI
PD64084
14.2 System Configuration and Control Method
14.2.1 Selecting video signal input path
When a video signal is input from a tuner or external pin, the input path of the video signal must be selected. This selection is made by a serial bus register of the PD64084. If the signal is input from a tuner when the ghost reducer is used, a digital video signal input pin is selected by the PD64084. When signals are input from other external pins (such as those of a VCR, DVD, video camera, or game machine), the internal A/D converter of the PD64084 is made valid, so that the video signal directly input to the PD64084 becomes valid. For details on how to set the pins and registers, see Table 14-1 and Table 14-2 in Section 14.3. 14.2.2 Selecting mode according to clock and video signal input path When the PD64031A and PD64084 are digitally connected directly, the system clock must be shared by the two ICs. When the ghost reducer is used (when signals are input from a tuner), the PD64031A generates burst lock clock fSC, as shown in Figure 14-1. This fSC goes through an external BPF and is input to the 8fSC PLL of the PD64084, where system clocks (8fSC and 4fSC) are generated. These system clocks are used by the PD64084, and are also supplied to the PD64031A by the PD64084 from the CLK8 pin. When the ghost reducer is not used (when signals are input from an external source), the video signal is not input to the PD64031A, and only the PD64084 operates. It is therefore necessary that the burst clock generated by the
PD64084 be used.
To switch the path of inputting fSC to the fSC BPF between the FSCO pin of the PD64031A and the FSCO pin of the
PD64084, an analog switch is necessary in the input block of the fSC BPF.
This analog switch is controlled by the WP1 pin of the PD64031A. The WP1 pin is controlled by register DIR3DYC (SA08h: D7 and D6) of the PD64031A (that selects a three-dimension Y/C separation digital connection mode). By changing the setting of this register depending on whether the ghost reducer is used or not, the analog switch can be controlled by the signal output from the WP1 pin. In this way, the fSC path can be changed. A 20-MHz crystal oscillator that generates the basic clock for the fSC generator should be provided to the PD64031A. When the ghost reducer is not used and the PD64084 operates alone, the 20-MHz clock output from the C20O pin of the PD64031A is used. For details on how to set the pins and registers, see Table 14-1 and Table 14-2 in Section 14.3.
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Data Sheet S16021EJ2V0DS
PD64084
14.3 Setting of Digital Direct-Connected System
14.3.1 Hardware setting See the pin connection and setting in the following table to digitally connect the PD64031A and PD64084 directly. Table 14-1. Pin Setting for Digital Direct-Connection
PD64031A Pin
DO9 to DO0 (pins 6 to 15) N3D (pin 3) Signal Direction DYCO0 to DYCO9 (pins 63 to 72) LINE (pin 74) 10-bit digital video signal interface Three-dimension processing prohibiting flag Register N3D1STEN of the PD64031A (SA01h: D5) must be set. CSO (pin 4) CSI (pin 77) Composite sync signal The signal from the sync separation circuit connected to the PD64031A is shared by the
PD64084 Pin
Function
PD64084.
ALTF (pin 5) ALTF (pin 73) Digital clamp clock (4fSC) Register ADCLKS of the PD64084 (SA15h: D7 and D6) must be set. OCP (pin 18) ST0 (pin 59) Clamp pulse for digital clamp circuit Register ST0S of the PD64084 (SA07h: D1 and D0) must be set. CLK8 (pin 30) CLK8 (pin 57) System clock (8fSC) Register CLK8OFF of the PD64084 (SA07h: D4) must be set. FSCO (pin 47) C20O (pin 54) CKMD (pin 31) WP1 (pin 35) - - FSCI (pin 54) XI (pin 36) - - Burst lock clock (connected via an analog switch) 20-MHz reference clock Fixed to high level (external clock mode) Connected to analog switch (control signal output) This pin is controlled by register DIR3DYC of the PD64031A (SA08h: D7 and D6) to select a clock path. EXDAS (pin 58) FSCI (pin 40) - - - - - - FSCO (pin 51) XO (pin 37) - - Fixed to high level (digital output is valid) Fixed to GND (fSC generator is not used) Connected to analog switch Open
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Data Sheet S16021EJ2V0DS
PD64084
14.3.2 Register setting Correctly set the following registers when digitally connecting the PD64031A and PD64084 directly. Also refer to the following table for register setting to specify whether the ghost reducer is used or not. Table 14-2. Register Setting
Register With Ghost Reducer Used With Ghost Reducer Not Used Remark
PD64031A
EXDAS (SA01h: D7) N3D1STEN (SA01h: D5) CLK20LOW (SA01h: D2) ADCPMD (SA04h: D5, D4) DIR3DYC (SA08h: D7, D6) DCPAG (SA08h: D5 to D3) DCPEN (SA09h: D6) DCPLPFS (SA09h: D5) DCPVEN (SA09h: D4) DCP_TEST (SA09h: D3 to D0) 10 101 1 1 1 1111 Don't care Don't care Don't care Don't care Don't care 1 1 0 Don't care Don't care Don't care 10 11 Digital data output setting 3-dimesnion processing prohibiting flag setting 20-MHz clock output setting ADC input bias mode setting Mode selection (WP1 pin control) Digital clamp characteristic setting Digital clamp selection Error calculation block LPF selection Clamp timing setting Permissible error range during clamping
PD64084
EXADINS (SA02h: D5) CLK8OFF (SA07h: D4) ST0S (SA07h: D1, D0) ADCLKS (SA15h: D7, D6) HIZEN (SA16h: D4) 01 01 1 1 0 Don't care 11 0 Internal ADC selection 8fSC output setting Clamp pulse output setting ALTF clock delay setting Digital input / output status select
35
Data Sheet S16021EJ2V0DS
PD64084
15. I C BUS INTERFACE 15.1 Basic Specification
The I2C bus is a two-wire bi-directional serial bus developed by Philips. It consists of a serial data line (SDA) for communication between ICs and a serial clock line (SCL) for establishing sync in communication. Figure 15-1. I2C Bus Interface
3.3 V supply voltage Serial data line Serial clock line
2
SDA Master IC SCL
SDA Slave IC SCL
SDA Slave IC SCL
The following procedure is used to transfer data from the master IC to a slave IC. <1> Start condition : To start communication, hold the SCL at a high level, then pull down the SDA from a high to a low level. <2> Data transfer : To transfer data, pull up the SCL from a low to a high, while holding the current state of the SDA. Data transfer is carried out in units of 9 bits, that is, 8 data bits (D7 to D0, MSB first) plus an acknowledgment bit (ACK). A selected slave IC sets the SDA to a low when it receives bit 9 to send acknowledgment. <3> Stop condition : To terminate communication, pull up the SDA from a low to a high upon acknowledgment, while keeping the SCL at a high. Figure 15-2. Start Condition, Data Transfer, and Stop Condition Formats
Start condition 0.6 s MIN. SCL 0.1 s 0.1 s MIN. MIN. SDA (Master) D7 D6 D5 D4 D1 D0 Hi-Z D7 D0 Hi-Z 1.3 s 0.6 s MIN. MIN. 0 ns MIN. Data acceptance Stop condition 0.6 s MIN.
SDA (Slave)
ACK
ACK
36
Data Sheet S16021EJ2V0DS
PD64084
15.2 Data Transfer Formats
Immediately when the master IC satisfies the start condition, each slave receives a slave address. If the received slave address matches that of a slave IC, communication begins between the slave IC and the master IC. If not, the SDA line is released. Two sets of slave addresses can be specified according to the SLA pin. Table 15-1. Slave Address
SLA pin setting (Unchangeable when power is on) L or open H
Slave address Write mode B8h (1011 1000b) BAh (1011 1010b) Read mode B9h (1011 1001b) BBh (1011 1011b)
(1) Write mode formats (reception mode for slaves) If a slave IC receives its write-mode slave address in byte 1, it continues to receive a subaddress in byte 2 and data in the subsequent bytes. The subaddress auto-increment function enables continuous data reception. Figure 15-3. Write Mode Formats (a) One-byte write format
Start Slave Address 8 bits WA 1 bit Sub Address n 8 bits A Data (Sub Address n) A Stop 1 bit 8 bits 1 bit
(b) Multiple-byte write format
Start Slave Address 8 bits WA 1 bit Sub Address n 8 bits A Data (Sub Address n) A Data (Sub Address n+1) A 1 bit 8 bits 1 bit 8 bits 1 bit
A Data (Sub Address 17h) A Stop 1 bit 8 bits 1 bit
Remark
Start : Start condition W A : Write mode specification (= 0) : Acknowledgment XXX : Master Device
Stop : Stop condition R N
Sr
: Restart condition
: Read mode specification (= 1)
: No-acknowledgment XXX : Slave Device ( PD64084)
37
Data Sheet S16021EJ2V0DS
PD64084
(2) Read mode format (transmission mode for slaves) If a slave IC receives its read-mode slave address in byte 1, it sends data in byte 2 and the subsequent bytes. No subaddress is specified in this mode. Transmission begins always at address 0. Before establishing a stop condition, the master IC must send no-acknowledgment and release the SDA line. Figure 15-4. Read Mode Format (a) Single read format
Start Slave Address 8 bits R A Data (Sub Address 0) A Data (Sub Address 1) A 1 bit 8 bits 1 bit 8 bits 1 bit A Data (Sub Address n) N Stop 8 bits 1 bit
(b) Multiple read format
Start Slave Address 8 bits WA 1 bit Sub Address n 8 bits A Sr 1 bit Slave Address 8 bits R A Data (Sub Address n) A 1 bit 8 bits 1 bit
A Data (Sub Address 06h) N Stop 1 bit 8 bits 1 bit
Remark
Start : Start condition W A : Write mode specification (= 0) : Acknowledgment XXX : Master Device
Stop : Stop condition R N
Sr
: Restart condition
: Read mode specification (= 1)
: No-acknowledgment XXX : Slave Device ( PD64084)
15.3 Initialization
The serial bus registers are initialized when the PD64084 is reset (RSTB). The I2C bus interface become operative after 100 s from reset operation. In addition, its write register is previously loaded with an initial value. For the reset operation, refer to 2.4 Start-up of Power Supply and Reset.
38
Data Sheet S16021EJ2V0DS
PD64084
15.4 Serial Bus Registers
The PD64084 incorporates twenty-four 8-bit write registers and seven 8-bit read registers. Writing to the write registers is possible in the write mode (with a slave in reception mode), while reading from the read registers is possible in the read mode (with a slave in transmission mode). The following table lists how each serial bus register is mapped. (1) Write register mapping Slave address: 10111000b = B8h (SLA0 = L), 10111010b = BAh (SLA0 = H)
Data Map (SA00-SA17) SA 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 ADCLKS SYSPDS CNROFS HCNTFSYN SHT0 HPLLFS 0 0 0 YHCOR SHT1 BPLLFS HSSL BGPS ADPDS EXTDYCO ADCLPFSW NSDSW HIZEN ADCLPSTP NRZOFF VLSEL 0 0 V1PSEL 0 0 1 WSS YNRK ID1ON WSC ID1DECON VAPGAIN 0 YPFT VEGSEL SELD1FL 0 0 YHCGAIN VCT FSCFG 0 0 0 ED2OFF OTT PLLFG CC3N 0 1 0 OVST CLKG2D C0HS 1 0 1 CSHDT CLKGGT KILR VSSL BGPW FSCOFF VLTYPE 0 0 0 VTVH 0 0 0 D7 0 CLKS DYCOS CPP DYCOR DCCOR YNRINV ID1W0A1 YNRLIM ID1W0A2 CLK8OFF CNRK ST1S VTRR FELCHK VAPINV YPFG CLPH 0 0 0 KCTT CLKGEB CLKGT SELD2FH 1 0 0 TT D6 NRMD D5 0 NSDS EXADINS MFREEZE HDP DYGAIN DCGAIN CNRINV CNRLIM ST0S LDSR VFLTH D4 1 D3 COUTS MSS PECS CDL D2 D1 YAPS KILS EXCSS D0
VTRH TH
Caution
It may be necessary to change set values on the serial bus depending on the results of performance evaluation conducted by NEC Electronics.
39
Data Sheet S16021EJ2V0DS
PD64084
(2) Read register mapping Slave address: 10111001b = B9h (SLA0 = L), 10111011b = BBh (SLA0 = H)
Data Map (SA00 - SA06) SA 00 01 02 03 04 05 06 DCLEVH CRCCH DCFEL ED2 B10 B3 B11 B4 B12 ID1W0 ID1W2 CRCCFEL HOLD1 B5 B13 D7 VER D6 D5 D4 KILF WSL B6 B14 B7 B15 ID1W1 B8 B16 B9 B17 D3 NSDF D2 LDSDF D1 OVSDF D0 OHSDF
40
Data Sheet S16021EJ2V0DS
PD64084
15.5 Serial Bus Register Functions
Table 15-2 lists the function of each write register. The initial and typical values for each register were determined for evaluation purposes by NEC Electronics. They are not necessarily optimum values. (1) Write Register Table 15-2. Write Register Functions (1/14)
SA Bit Name and function Description Typical value 00 D7 D6 NRMD Specifies an operation mode. Undefined 0 : YCS mode :
Comp.
Initial value 0 0
0 Y/C separation (burst locked clocking)
ADC 4fSC YCS (3D/2D) DAC DAC Y C
-
Memory
1 : YCS+ mode :
Comp.
2D Y/C separation and YNR/CNR (burst locked clocking)
ADC 4fSC YCS (2D) YNR CNR Memory DAC DAC Y C
D5-D4 D3-D2 COUTS
Specifies the way the C signal is output. (Common to digital and analog outputs)
Undefined 00: Input-to-output gain of 2, without BPF processing 01: Input-to-output gain of 2, with BPF processing 10: Input-to-output gain of 1, without BPF processing 11: Input-to-output gain of 1, with BPF processing 00: Correction is disabled for both analog and digital outputs. 01: Correction is enabled for only analog outputs. 10: Correction is enabled for only digital outputs. 11: Correction is enabled for both analog and digital outputs.
01 11
01 11
D1-D0
YAPS Specifies Y signal output correction. (Vertical aperture compensation and Y peaking filtering)
11
11
41
Data Sheet S16021EJ2V0DS
PD64084
Table 15-2. Write Register Functions (2/14)
SA Bit Name and function Description Typical value 01 D7-D6 CLKS Specifies whether to force use of the system clock. 00: Automatic setting (in an operation mode specified by NRMD) 01: Forced burst locked clocking 1x: Forced line (horizontal) locked clocking Caution If the specified setting does not match the input signal, a malfunction may occur. D5-D4 NSDS Specifies whether to force standard/nonstandard signal processing. 00: Adaptive processing (performed according to whether a nonstandard signal is detected) 01: Forced standard signal processing (performed regardless of whether a nonstandard signal is detected) 10: Forced horizontal sync nonstandard signal processing 11: Forced vertical sync nonstandard signal processing (forced inter-line processing) Caution If the specified setting does not match the input signal, a malfunction may occur. D3-D2 MSS Specifies whether to force inter-frame or interline processing. 00: Adaptive processing (performed according to the LINE pin input and motion detection signal) 01: Forced inter-frame processing (performed according to the LINE pin input) 1x: Forced inter-line processing D1-D0 KILS Specifies whether to force killer processing 00: Adaptive processing (performed according to the KIL pin input and internal killer detection results) 01: Internal killer detection is not used (processing is performed according to the KIL pin input only). 1x: Forced killer processing In killer processing, subtraction of the C signal from Comp. Signal is disabled. 01 01 00 00 00 00 00 Initial value 00
42
Data Sheet S16021EJ2V0DS
PD64084
Table 15-2. Write Register Functions (3/14)
SA Bit Name and function Description Typical value 02 D7-D6 DYCOS Specifies DYCO pin input/output. In case of EXTDYCO = 0 00: Y/C separation signal alternate output 01: Test mode (setting prohibited) 1x: Low* High impedance In case of EXDYCO = 1 00: DYCO9-0 : Output, EXTDYCO9-0 : Input (When EXADINS=0, Low Note) 01: Test mode (setting prohibited) 1x: DYCO9-0 : Input (When EXADINS=0, Low Note), EXTDYCO9-0 : Output Note If HIZEN (SA16h, D4) = 1, then HI-Z. D5 EXADINS Specifies whether to select external ADC. D4 MFREEZE External memory test bit D3-D2 PECS 0: Internal ADC 1: External ADC (digital video signal, converted from analog form, is input to the DYCO9 to DYCO0 pins) 0: Normal mode 1: Test mode (setting prohibited) 00: Normal setting 00 00 0 0 0 0 10 Initial value 10
Specifies a pedestal error 01: Test setting (setting prohibited) correction test bit. 10: Test setting (setting prohibited) 11: Test setting (setting prohibited) D1-D0 EXCSS Specifies whether to use external C sync input. 00: Internally separated sync signal is always used (CSI input is not used). 01: Sync signal input at the CSI pin is used during out-of-sync state. 1x: Sync signal input at the CSI pin is always used. 03 D7 D6 CPP Undefined 0: 2.2 s 1.1 s 100 100 0 0 0 0 01 01
Specifies the clamp pulse 1 : width of internal ADC D5-D3 HDP Fine adjustment of system horizontal phase D2-D0 CDL Fine adjustment of C signal output delay
000: -1.12 s to 100: 0.00 s (Typ.) to 111: +0.84 s Fine-adjusts the horizontal-processing phase with respect to the horizontal sync signal (0.28 s/step). 000: -280 ns to 100: 0 ns (Typ.) to 111: +210 ns Fine-adjusts the C signal phase with respect to the Y signal (70 ns/step).
100
100
43
Data Sheet S16021EJ2V0DS
PD64084
Table 15-2. Write Register Functions (4/14)
SA Bit Name and function Description Typical value 04 D7-D4 DYCOR DY detection coring level (Y motion detection coring) 0000: Coring 0 (Closer to motion pictures) to 0010 Initial value 0010
1111: Large amount of coring (Closer to still pictures) The coring level for inter-frame Y difference detection is specified. A signal smaller than specified is assumed to be noise, resulting in '0' being output. 0000: Gain of 0 (Closer to still pictures) to 1111: Maximum gain (Closer to motion pictures) Inter-frame Y difference detection gain is specified. 0000: Coring 0 (Closer to motion pictures) to 0011 0011 1001 1001
D3-D0
DYGAIN DY detection gain (Y motion detection gain)
05
D7-D4
DCCOR DC detection coring level (C motion detection coring)
1111: Large amount of coring (Closer to still pictures) The coring level for inter-frame C difference detection is specified. A signal smaller than specified is assumed to be noise, resulting in 0 being output. 0000: Gain of 0 (Closer to still pictures) to 0110 0110
D3-D0
DCGAIN DC detection gain (C motion detection gain)
1111: Maximum gain (Closer to motion pictures) Inter-frame C difference detection gain is specified.
44
Data Sheet S16021EJ2V0DS
PD64084
Table 15-2. Write Register Functions (5/14)
SA Bit Name and function Description Typical value 06 D7 YNRK Specifies the frame recursive YNR nonlinear filter gain. D6 YNRINV Specifies the frame recursive YNR nonlinear filter convergence level. D5-D4 YNRLIM Specifies the frame recursive YNR nonlinear filter limit level. 0: 6 LSB (small noise reduction effect and small after-image) 1: 8 LSB (large noise reduction effect and large after-image) An input larger than specified is assumed to be a motion component, resulting in 0 being output. 00: 0 LSB (YNR off) to 11: 3 LSB (large noise reduction effect and large after-image) An input larger than specified is assumed to be a motion component, resulting in a limit value being output. Nonlinear characteristic curve based on YNRK, YNRINV, and YNRLIM
Y' output (LSB) YNRINV=1 4 YNRINV=0 3 2 -8 -6 1 -1 -3 -4 6 8 YNRK=1 (k=7/8) YNRK=0 (k=6/8) YNRLIM=3 YNRLIM=2 YNRLIM=1 Y input (LSB)
Initial value 0
0: x 6/8 (small noise reduction effect and small after-image) 1: x 7/8 (large noise reduction effect and large after-image) The magnitude of the NR effect is specified.
0
0
0
01
01
-2 Remarks1. The Characteristic are
symmetrical with respect to the origin. 2. The levels shown are in 8-bit terms.
D3
CNRK Specifies the frame recursive CNR nonlinear filter gain.
0: x 6/8 (small noise reduction effect and small after-image) 1: x 7/8 (large noise reduction effect and large after-image) The magnitude of the NR effect is specified. 0: 6 LSB (small noise reduction effect and small after-image) 1: 8 LSB (large noise reduction effect and large after-image) An input larger than specified is assumed to be a motion component, resulting in 0 being output. 00: 0 LSB (CNR off) to 11: 3 LSB (large noise reduction effect and large after-image) An input larger than specified is assumed to be a motion component, resulting in a limit value being output. Nonlinear characteristic curve based on CNRK, CNRINV, and CNRLIM
C' output (LSB) CNRINV=1 4 CNRINV=0 3 2 -8 -6 1 -1 -3 -4 6 8 CNRK=1 (k=7/8) CNRK=0 (k=6/8) CNRLIM=3 CNRLIM=2 CNRLIM=1 C input (LSB)
0
0
D2
CNRINV Specifies the frame recursive CNR nonlinear filter convergence level.
0
0
D1-D0
CNRLIM Specifies the frame recursive CNR nonlinear filter limit level.
01
01
-2 Remarks1. The Characteristic are
symmetrical with respect to the origin. 2. The levels shown are in 8-bit terms.
45
Data Sheet S16021EJ2V0DS
PD64084
Table 15-2. Write Register Functions (6/14)
SA Bit Name and function Description Typical value 07 D7 ID1ENON Specifies whether to superimpose ID-1 specification ID signal. D6 ID1ENW0A1 Specifies whether to set bit A1 of ID-1 word 0. D5 ID1ENW0A2 Specifies whether to set bit A2 of ID-1 word 0. D4 CLK8OFF Specifies the state of the CLK8 pin output. D3-D2 ST1S Specifies internal signal monitor output for the ST1 pin. D1-D0 ST0S Specifies internal signal monitor output for the ST0 pin. 00: I2C SDA inversed pulse 01: Internal ADC clamp pulse (active-high) 10: Composite sync (active-low) 11: H sync (active-high) 00: Reserved 01: External ADC clamp pulse (active-high) 10: HV blanking (active-high) 11: V sync (active-low) 00 00 0: Active-low (to output 8fSC clock pulse) 1: Fixed to low level (to reduce radiation noise) 1 0 0: 0 (image display format = normal) 1: 1 (image display format = letter box) 0 0: 0 (transmission aspect of 4:3) 1: 1 (transmission aspect of 16:9) 0 0: Through (no superimposition) 1: Forced superimposition Caution Do not set this bit to 1 during no-signal state. Initial value 0
46
Data Sheet S16021EJ2V0DS
PD64084
Table 15-2. Write Register Functions (7/14)
SA Bit Name and function Description Typical value 08 D7-D6 WSC Specifies the amount of noise detection coring. 00: 0LSB (high detection sensitivity) 01: 1LSB 10: 2LSB 11: 3LSB (low detection sensitivity) Specifies an input coring value for the noise detection circuit. Detection results are not used within the device. D5-D4 VTRH Specifies hysteresis for horizontal sync nonstandard signal detection (out-ofhorizontal sync intra-field) 00: Hysteresis off (width of 0 clock pulses) 01: Low hysteresis (width of 2 clock pulses) 10: Medium hysteresis (width of 4 clock pulses) 11: High hysteresis (width of 6 clock pulses) For horizontal sync nonstandard signal detection, a criterion value to detect an out-of-horizontal sync state intra-field is decreased by a value indicated above. D3-D2 VTRR Specifies sensitivity for horizontal sync nonstandard signal detection (out-ofhorizontal sync intra-field) 00: High detection sensitivity (width of 4 clock pulses) 01: Medium detection sensitivity (width of 8 clock pulses) 10: Low detection sensitivity (width of 12 clock pulses) 11: Detection off If the degree of out-of-horizontal sync state intra-field becomes larger than specified, a horizontal sync nonstandard signal is assumed to have been detected. Horizontal sync nonstandard signal detection characteristic curve
Standard-to-nonstandard hysteresis width VTRHx2(clk) Note 1 OHSD=1 (nonstandard signal detected) OHSD=0 (standard signal detected) Notes 1. clk is in 4fSC units. 2. Excluding when VTRR = 11
Initial value 01
01
01
01
01
01
Standard-to-nonstandard decision criterion Note 2 (VTRR+1)x4(clk) Note 1
D1-D0
LDSR Specifies sensitivity for frame sync nonstandard signal detection (out-ofhorizontal sync interframe)
00: High detection sensitivity (width of 0.5 clock pulses) 01: Medium detection sensitivity (width of 1 clock pulse) 10: Low detection sensitivity (width of 1.5 clock pulses) 11: Detection off If the degree of out-of-horizontal sync state inter-frame becomes larger than specified, a frame sync nonstandard signal is assumed to have been detected.
10
10
47
Data Sheet S16021EJ2V0DS
PD64084
Table 15-2. Write Register Functions (8/14)
SA Bit Name and function Description 0 : Normal ( PD64082 compatible) 1 : fsc trap Typical value 09 D7 WSS Specifies the pre-filter characteristic of noise detection. D6 ID1DECON ID-1 decoder 0 : disable 1 : enable When decoding is disable, The output of register is following. WORD0=00, WORD1=1111, WORD2=00h D5-D4 TH ID-1 decorder check level D3 FELCHK ID-1 decoder Field check enable D2-D1 TT ID-1 decoder pulse width level D0 VFILTH Specifies the vertical blanking (1H to 22H) BPF 0A D7-D5 VAPGAIN Specifies a vertical aperture compensation gain. D4-D0 VAPINV Specifies a vertical aperture compensation convergence point. 00000: Correction off to 11111: Maximum correction Vertical aperture compensation characteristic curve based on VAPGAIN and VAPINV
Output Coring: Fixed at 1 -VAPINV Tilt: VAPGAIN/8Note
Initial value 0
0
1
1
01 : Strict 00 10 : :
00
00
11 : Loose 0 : 6 fields check is disable 1 : 6 fields check is enable 00 : 8CLK 01 : 2CLK 10 : 4CLK 11 : 16CLK 0: BPF enable 1: BPF disable (through) 0 0 00 00 1 1
000: Correction off to 111: Maximum correction (0.875 times)
-
000
-
00000
Tilt: Fixed at -1 Input VAPINV Note The curve is symmetrical with resept to the origin
48
Data Sheet S16021EJ2V0DS
PD64084
Table 15-2. Write Register Functions (9/14)
SA Bit Name and function Description Typical value 0B D7 TEST Test bit D6 TEST Test bit D5-D4 YPFT Specifies the Y peaking filter (BPF) center frequency.
Gain Y-peaking filter BPF characteristic curve 1.25 1.13 1.00 0.88 0.75 0.63 k=0 0.50 k=1 0.38 k=2 0.25 k=3 0.13
Initial value 0
0: Normal mode 1: Test mode (setting prohibited) 0: Normal mode 1: Test mode (setting prohibited) 00: 3.58 MHz, 01: 3.86 MHz, 10: 4.08 MHz, 11: 4.22 MHz
0
0
0
11
11
0.89
1.79
2.68
3.58
4.47
5.37
6.26
f (MHz)
D3-D0
YPFG Specifies a Y peaking filter gain.
0000: -1.0 times to 1000: 0.0 times to 1111: +0.875 times Y signal output frequency characteristic curve based on YPFT and YPFG
Output 1.875 1.5 1.0 0.5 YPFG=4 YPFG=0 0.5fSC fSC 1.5fSC Input freq. YPFT=2 YPFT=0 YPFG=15 YPFG=12 YPFG=8
7.16
0.00
1000
1000
0
49
Data Sheet S16021EJ2V0DS
PD64084
Table 15-2. Write Register Functions (10/14)
SA Bit Name and function Description Typical value 0C D7-D6 V1PSEL 00: Suppression off 10 Initial value 10
Line comb filter horizontal 01: Low suppression level dot interference 10: Medium suppression level suppression level 11: High suppression level Horizontal dot interference is reduced at inter-line Y/C separation. D5-D4 VEGSEL Line comb filter vertical dot interference suppression level 00: Suppression off 01: Low suppression level 10: Medium suppression level 11: High suppression level Vertical dot interference is reduced at inter-line Y/C separation. D3 CC3N Selects a line comb filter C separation filter characteristic. D2 C0HS Specifies C signal delay time extension at NR D1 CLPH ADC clamp test bit D0 SELD2FH Specifies DC detection High-frequency sensitivity. 0D D7 D6 D5 SELD1FL Specifies DY detection low-frequency sensitivity. D4 D3 D2-D0 0E D7-D4 D3-D0 0F D7-D4 D3-D0 0 0 101 0000 1000 0100 0100 0 0 101 0000 1000 0100 0100 0 0 101 0000 1000 0100 0100 0 0 0: Low sensitivity, Closer to still pictures 1: High sensitivity, Closer to motion pictures 0 0 0 0 0 0 0: Normal mode 1: Test mode (setting prohibited) 0: Low sensitivity, Closer to still pictures 1: High sensitivity, Closer to motion pictures 0 0 0 0 0: 1H delay 1: No 1H delay 0 0 0: Narrow bandwidth 1: Wide bandwidth 0 0 10 10
50
Data Sheet S16021EJ2V0DS
PD64084
Table 15-2. Write Register Functions (11/14)
SA Bit Name and function Description Typical value 10 D7-D6 YHCOR Specifies Y output high frequency component coring. 00: Coring off 01: Small amount of coring (1 LSB: 8-bit terms) 00 Initial value 00
10: Medium amount of coring (2 LSB: 8-bit terms) 11: Large amount of coring (3 LSB: 8-bit terms)
Coring characteristic curve (for high-frequency component only)
Solid line: YHCGAIN = 0 Dotted line: YHCGAIN = 1 Output (LSB)
-YHCOR Input (LSB) YHCOR Remark Converted into 8 bits
D5
YHCGAIN Specifies Y output highfrequency component coring gain.
0: Normal (x1) 1 :1/2 gain Refer to YHCOR (SA10h, D7-D6)
0
0
D4
ED2OFF Specifies WCV-ID detection circuit.
0: Normal mode 1: Forced WCV-ID detection circuit turned off 0: Normal mode 1: Test mode 0: Normal mode 1: Test mode 0x: Normal mode 1x: Test mode
0
0
D3
OVST Nonstandard signal detection test bit
0
0
D2
CSHDT H / V counter test bit
0
0
D1-D0
KCTT H / V counter test bit
00
00
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Data Sheet S16021EJ2V0DS
PD64084
Table 15-2. Write Register Functions (12/14)
SA Bit Name and function Description Typical value 11 D7 SHT1 Nonstandard signal detection test bit D6 SHT0 Nonstandard signal detection test bit D5 VCT H / V counter test bit D4 OTT H / V counter test bit D3 CLKG2D Clock generator section test bit D2 CLKGGT Clock generator section test bit D1 CLKGEB Clock generator section test bit D0 CLKGT Clock generator section test bit 12 D7 HPLLFS Specifies the horizontal PLL filter. D6 BPLLFS Specifies the burst PLL filter. D5 FSCFG Specifies the burst extraction gain. D4 PLLFG Specifies the PLL loop gain. D3-D0 KILR Killer detection reference 0000: Detection off 0001: Low detection sensitivity 1111: High detection sensitivity 13 D7-D4 HSSL Horizontal sync slice level D3-D0 VSSL Vertical sync slice level 0000: HSSL setting + 0LSB 1111: HSSL setting + 15LSB (in 8-bit input terms, 1LSB/step) to 1000 1000 0000: 4LSB to 1111: 19LSB 1111 1111 to 0010 1010 0: Low gain (slow convergence) 1: High gain (quick convergence) 1 1 0: High gain 1: Low gain 0 0 0: Quick convergence 1: Slow convergence 1 1 0: Slow convergence 1: Quick convergence 1 0: Normal mode 1: Test mode 0 0 0: Normal mode 1: Test mode 0 0 0: Normal mode 1: Test mode 0 0 0: Normal mode 1: Test mode 0: Normal mode 1: Test mode 0: Test mode 1: Normal mode 1 1 0 0 0 0 0: Normal mode 1: Test mode 0 0 0: Normal mode 1: Test mode 0 Initial value 0
(in 8-bit input terms, 1LSB/step)
52
Data Sheet S16021EJ2V0DS
PD64084
Table 15-2. Write Register Functions (13/14)
SA Bit Name and function Description 0000: H sync center + 2 s to 1111: H sync center + 5.75 s Calculation of gate start position from the H sync center : 0.25 x BGPS + 2.0 (s) 0000: 0.5 s to 1111: 4.25 s Calculation of gate width : 0.25 x BGPW + 0.5 (s) 00: 0 ns typically (setting prohibited) 01: 3 ns typically 10: 17.5 ns typically 11: 20.5 ns typically D5 ADPDS Specifies whether to use ADC power-down. D4 NRDSW Nonstandard detection section test D3 NRZOFF WCV-ID detection NRZ section check D2 FSCOFF WCV-ID detection FSC section check D1-D0 VTVH Specifies WCV signal noimage section processing (only letter box signal is valid). 00: Ordinary processing 01: Forced inter-frame Y/C separation 10: Forced inter-line Y/C separation 11: Forced through (composite signal is output.) 00 00 0: FSC amplitude check on 1: FSC amplitude check off 0 0 0: NRZ section amplitude check on 1: NRZ section amplitude check off 0 0 0: Normal mode 1: Test mode 0 0 0: Do not stop operation of ADC not in use.( High current drain) 1: Stop operation of ADC not in use. (Low current drain) 1 1 11 11 0011 0011 Typical value 14 D7-D4 BGPS Specifies the internal burst gate start position. 0101 Initial value 0101
D3-D0
BGPW Specifies the internal burst gate width.
15
D7-D6
ADCLKS Specifies the ADC clock delay.
53
Data Sheet S16021EJ2V0DS
PD64084
Table 15-2. Write Register Functions (14/14)
SA Bit Name and function Description Typical value 16 D7-D6 SYSPDS System power down 00: Normal operation 01: Mode1 (D/A, Memory Access stop, Total current :mid) 10: Mode2 (Memory Access stop, Total current: High 11: Mode3 (A/D, D/A, Memory Access stop, Total current : Low) Remark All register data are kept in power down term.Reset is not required for re-start. D5 EXTDYCO Extended digital I/O enable D4 HIZEN Digital input / output status select D3 VLSEL Test bit D2 VLTYPE Test bit D1 D0 17 D7 CNROFS CNR section test bit D6 HCNTFSYN Nonstandard signal detection test bit D5 ADCLPFSW ADC clamp test bit D4 ADCLPSTP ADC clamp test bit D3-D0 Undefined 0000 0000 0: Normal mode 1: Clamp disable 0 0 0: Normal mode 1: Test mode 0: Normal mode 1: Test mode Undefined Undefined 0: Normal mode 1: Test mode 0: Normal mode 1: Test mode (Forced H counter synchronize) Do not use "1" setting in the YCS mode. 0: Normal mode 1: Clamp level feedback disable 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0: Low 1: Hi-Z 0 0 0: EXTDYCO9-EXTDYCO0 disable 1: EXTDYCO9-EXTDYCO0 enable 0 0 00 Initial value 00
54
Data Sheet S16021EJ2V0DS
PD64084
(2) Read Register Table 15-3. Read Register Functions (1/2)
SA Bit Name and function Description Version code of PD64084 is `01'(Fixed) KILF Killer detection flag D3 NSDF Horizontal sync signal detection flag D2 LDSDF Frame sync nonstandard signal detection flag D1 OVSDF Vertical sync nonstandard signal detection flag D0 OHSDF Horizontal sync nonstandard signal detection flag 01 D7-D0 WSL 00000000: Closer to low noise 0: Standard signal detected 1: Nonstandard signal detected (such as VCR ordinary playback signal) 0: Standard signal detected 1: Nonstandard signal detected (such as laser disc special playback signal) 0: Standard signal detected 1: Nonstandard signal detected (such as VCR special playback signal and home TV game signal) Undefined 0: Color signal detected 1: Killer signal (non-burst signal) detected 0: Sync signal detected 1: No sync signal detected Initial value 00 D7-D6 D5 D4 VER Product Version Code -
Noise level detection data 11111111: Closer to high noise 02 D7 ED2 WCV-ID signal detection flag D6-D0 B3-B9 WCV-ID signal decoding result 03 D7-D0 B10-B17 WCV-ID signal decoding result 04 D7-D6 D5-D4 ID1W0 Decoded Data of ID-1 WORD0 D3-D0 ID1W1 Decoded Data of ID-1 WORD1 05 D7-D0 ID1W1 Decoded Data of ID-1 WORD2 Decoded data of WORD0 (8 bits) 00h Decoded data of WORD0 (4 bits) 1111 Undefined Decoded data of WORD0 (2 bits) 00 0: Invalid (no WCV-ID signal detected) 1: Valid (WCV-ID signal detected) -
55
Data Sheet S16021EJ2V0DS
PD64084
Table 14-3. Read Register Functions (2/2)
SA Bit Name and function Description Initial value 06 D7 DCLEVH ID-1 Decode Reference signal detect D6 CRCCH ID-1 Decode CRC check D5 DCFEL ID-1 Decode Reference signal Field check D4 CRCCFEL ID-1 Decode CRC field check D3 HOLD1 ID-1 Decode signal availability check detection result D2-D0 Undefined 0 : Error 1 : Normal 0 : Error 1 : Normal 0 : Error 1 : Normal 0 : Error 1 : Normal 0 : Reference signal is not detected 1 : Reference signal is detected -
56
Data Sheet S16021EJ2V0DS
PD64084
16. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (TA = +25C Unless otherwise specified)
Parameter Digital section supply voltage Analog section supply voltage DRAM section supply voltage I/O section supply voltage Input voltage Output current Package allowable dissipation Symbol DVDD AVDD DVDDRAM DVDDIO VI IO PD When mounted on an epoxy-glass board (TA = +70 C, 100 mm x 100 mm, 2 layer, 1.6-mm thick) Operating ambient temperature Operating junction temperature Storage temperature TA TJ:MAX Tstg Device ambient temperature Upper limit to junction temperature 0 to +70 +125 -40 to +125 C C C 3.3 V-resistant input pins Conditions Rating -0.3 to +3.6 -0.3 to +3.6 -0.3 to +3.6 -0.3 to +4.6 -0.3 to +4.6 -10 to +10 964 Unit V V V V V mA mW
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Parameter Digital section supply voltage Analog section supply voltage DRAM section supply voltage I/O section supply voltage High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage Reference clock input frequency Reference clock input amplitude Subcarrier input frequency Subcarrier input amplitude Composite Video signal input amplitude Composite signal Sync. signal input amplitude VAYI(S) Symbol DVDD AVDD DVDDRAM DVDDIO VIH VIL VIH VIL fXI VXI fFSCI VFSCI VAYI AYI pin, Picture + Sync. amp. (140 IREp-p), AVDD = 2.5 V AYI pin, Sync. amp. (40 IREp-p), AVDD = 2.5 V 229 (0 dB) 288 (+2 dB) mVp-p FSCI pin 0.45 0.8 XI pin Schmitt input pin 3.3 V-resistant buffer Conditions MIN. 2.3 2.3 2.3 3.0 2.0 0 0.7 x DVDDIO 0 19.998 0.8 3.579545 AVDD 20.000 0.3 x DVDDIO 20.002 DVDDIO MHz Vp-p MHz Vp-p Vp-p V TYP. 2.5 2.5 2.5 3.3 MAX. 2.7 2.7 2.7 3.6 3.6 0.8 3.6 Unit V V V V V V V
57
Data Sheet S16021EJ2V0DS
PD64084
Digital Section DC Characteristics (DVDD = DVDDRAM = 2.5 0.2 V, DVDDIO = 3.3 0.3 V, DGND = DGNDRAM = 0 V, TA = 0 to +70C)
Parameter Digital section current drain Symbol DIDD DIDDRAM DIDDIO Input leakage current High-level input current Low-level input current High-level output current 1 Low-level output current 1 High-level output current 2 Low-level output current 2 Low-level output current 3 Output leakage current ILI IIH IIL IOH1 IOL1 IOH2 IOL2 IOL3 ILO N-ch. open drain 3.0 mA type Conditions DVDD and DGND pins DVDDRAM and DGNDRAM pins DVDDIO and DGND pins Ordinary input Pull-down type Pull-up type 6.0 mA type VI = DVDDIO or 0 V VI = DVDDIO VI = 0 V VOH1 = 2.4 V VOL1 = 0.4 V VOH2 = 2.4 V VOL2 = 0.4 V VOL3 = 0.4 V DGND +3.0 +6.0 -10 0 +10 +6.0 -2.0 -10 20 -200 MIN. TYP. 37 15 12 0 83 -83 MAX. 100 50 20 +10 200 -20 -6.0 Unit mA mA mA
A A A
mA mA mA mA mA
3-state, open drain VO = DVDDIO to
A
58
Data Sheet S16021EJ2V0DS
PD64084
Analog Section DC Characteristics (AVDD = 2.5 0.2 V, AGND = 0 V, TA = +25C Unless otherwise specified)
Parameter Analog section current drain ADC resolution ADC integral linearity error ADC differential linearity error ADC differential gain ADC differential phase ADC reference voltage(low) ADC reference voltage(high) ADC analog input range ADC clamp pin voltage ADC analog input capacitance DAC resolution DAC integral linearity error DAC differential linearity error DAC differential gain DAC differential phase DAC full-scale output voltage DAC zero-scale output voltage DAC output amplitude fSC DAC resolution Symbol AIDD RESADY ILEADY DLEADY DGADY DPADY VRBADY VRTADY VINAY VCLY CINAD RESDA ILEDA DLEDA DGDA DPDA VFSDA VZSDA VOPPDA RESFSC FSCO pin AYO and ACO pins, AVDD = 2.5 V 1.77 0.77 AVDD = VIN = 0 V, fIN = 1 MHz AYO and ACO pins, AVDD = 2.5 V, fS = 4fSC DGAD, DPAD : NTSC 100 IRE RAMP Conditions AVDD and AGND pins AYI pin, AVDD = 2.5 V, fS = 4 fSC, DGAD, DPAD : NTSC 100 IRE RAMP MIN. TYP. 50 10 3.0 1.0 2.0 1.0 0.75 1.25 1.00 0.70 10 10 3.5 0.5 1.0 1.0 1.94 0.94 1.00 8 4.5 1.0 3.0 3.0 2.08 1.07 MAX. 100 6.0 2.0 3.0 3.0 Unit mA bit LSB LSB % Deg V V V V pF bit LSB LSB % deg V V Vp-p bit
59
Data Sheet S16021EJ2V0DS
PD64084
Digital Section AC Characteristics (DVDD = DVDDRAM = 2.5 0.2 V, DVDDIO = 3.3 0.3 V, DGND = DGNDRAM = 0 V, CL = 15 pF, tr = tf = 2 ns, TA = 0 to +70C)
Parameter Video data output delay Internal signal monitor output delay CSI input set-up time CSI input hold time ALTF output delay + DYCOn input set-up time ALTF output delay 0 ALTF output delay 1 ALTF output delay 2 ALTF output delay 3 DYCOn input set-up time DYCOn hold time Input capacitance tD:ALTF0 tD:ALTF1 tD:ALTF2 tD:ALTF3 tS:DYCO tH:DYCO CI tS:CSI tH:CSI CSI CLK8 CLK8 CSI : EXADINS = 1, ADCLKS = xx CLK8 ALTF : EXADINS = 1, ADCLKS = 00 CLK8 ALTF : EXADINS = 1, ADCLKS = 01 CLK8 ALTF : EXADINS = 1, ADCLKS = 10 CLK8 ALTF : EXADINS = 1, ADCLKS = 11 DYCOn CLK8 : EXADINS = 1 CLK8 DYCOn : EXADINS = 1 DVDD = VI = 0 V, fIN = 1 MHz
1/fCLK8OUT CLK8 tD:DAT ALTF (EXADINS=0) DYCO[9:0] (EXADINS=0) NSTD, ST1, ST0 tS:CSI CSI (input) ALTF (EXADINS=1) DYCO[9:0] (EXADINS=1) Hi-Z tD:DYCO-ALTF Hi-Z tD:ALTF tS:DYCO tH:DYCO tH:CSI
Symbol tD:DAT tD:STAT
Conditions CLK8 DYCOn, ALTF (EXADINS = 0) CLK8 NSTD, ST1, ST0
MIN. 3 35 0 15
TYP. 9 45
MAX. 20 55
Unit ns ns ns ns
tD:DYCO-ALTF CLK8 ALTF + : tS:DYCO 3 5 18 20 0 10 10
35 23 25 38 40
ns ns ns ns ns ns ns
15
pF
tD:STAT
60
Data Sheet S16021EJ2V0DS
PD64084
Clock and Timing Generation Section AC Characteristics (DVDD = DVDDRAM = AVDD = 2.5 0.2 V, DVDDIO = 3.3 0.3 V, DGND = DGNDRAM = AGND = 0 V, CL = 15 pF, TA = 0 to + 70C)
Parameter Subcarrier output frequency Subcarrier output amplitude Clock output frequency Clock output duty factor fSC pull-in range (in fSC terms) Horizontal sync attenuation (Capture range) Vertical sync attenuation (Capture range) Vvi Symbol fFSCO VFSCO fCLK8OUT DCLK8OUT fbp Vhi FSCO pin FSCO pin, AVDD = 3.3 V CLK8 pin, CKMD pin = DGND, CLK8OFF (SA07:D4) = 0 When the burst locked clock operation Sync input amplitude, HSSL = 1111, VSSL = 1000 (assumed to be 0dB when inputting 40IRE = 59LSB) -6 0 dB -8 45 Conditions MIN. TYP. 3.579545 1.00 28.63636 50 600 0 55 MAX. Unit MHz Vp-p MHz % Hz dB
ADC and DAC Section AC Characteristics (AVDD = 2.5 0.2 V, AGND = 0 V, CL = 15 pF, TA = +25 C)
Parameter ADC acquisition time Note DAC setting time
Note
Symbol tACKAD tSETDA
Conditions CLK8 AYI CLK8 AYO, ACO
MIN.
TYP. 7 15
MAX.
Unit ns ns
Note
Excluding data conversion delay
CLK8 tACKAD AYI tSETDA AYO, ACO
I2C Bus Interface Section AC Characteristics (DVDD = 2.5 0.2 V, DGND = 0 V, CL = 15 pF, TA = 0 to +70 C)
Parameter SDA pin ACK response delay SDA data set-up time SDA data hold time
SDA (Slave)
Symbol tACK tSU:DAT tHD:DAT
Hi-Z tACK
Conditions SCL SDA SDA:L SCL SCL SDA:Hi-Z
MIN.
TYP.
MAX. 500
Unit ns ns ns
100 0
tSU:DAT 9th Clock
tHD:DAT 1st Clock
SCL (from Master)
8th Clock
61
Data Sheet S16021EJ2V0DS
PD64084
17. APPLICATION CIRCUIT EXAMPLE
I/O block power supply (3.3 V)
I2C bus interface
System reset
0.1 F 0
22~33 pF 20 MHz X'tal 22~33 pF 0.1 F
BPF
0.1 F
10 F 0.1 F
AVDD 8fSC / RPLL 1820fH FSCI PLL AGND
0.01 F
AGND FSCO fSC / XO (455/2)fH Generator XI AVDD DVDD DGND
DVDDIO
RSTB SDA SCL SLA0
0.1 F 47 F
I2C bus interface
10 F 0.1 F
0.1 F x 2
0.1 F x 3 Clock mode (GND) 8fSC clock output States 0 [VD, etc.] States 1 [HD, etc.] Non standard detection Digital Y input Ext. ADC clock C-sync. input Forced 2D Killer input (option)
DGND x 4 DVDD x 3 CKMD CLK8 ST0 ST1 NSTD DYCO9-DYCO0 ALTF CSI LINE KIL
AVDD CBPC ACO C-DAC AYO Y-DAC CBPY AGND
DVDDRAM x 2 DGNDRAM x 2
PD64084
Internal memory
TEST01-TEST12 Open TEST13-TEST17 TEST18-TEST26 Open TESTIC1, TESTIC2
ADC 1F Analog comp. input 10 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F VCLY VRBY VRTY VCOMY AVDD AGND AYI
47 F
10 F 0.1 F 0.1 F
Analog block power supply (2.5 V)
Caution
This application circuit and the circuit parameters are for reference only, and not intended for use in actual design-ins.
62
Data Sheet S16021EJ2V0DS
Digital block power supply (2.5 V)
Analog C output Analog Y output
0.1 F
PD64084
18. PACKAGE DRAWING
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A B
75 76
51 50
detail of lead end S CD Q R
100 1
26 25
F G P H I
M
J K S
N
S L M
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 3 +7 -3 1.60 MAX.
S100GC-50-8EU, 8EA-2
63
Data Sheet S16021EJ2V0DS
PD64084
19. RECOMMENDED SOLDERING CONDITIONS
The PD64084 should be solderd and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, content an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 19-1. Surface Mounting Type Soldering Conditions * PD64084GC-8EA-ANote1: 100-pin plastic LQFP (fine pitch) (14 x 14 mm) * PD64084GC-8EA-YNote2: 100-pin plastic LQFP (fine pitch) (14 x 14 mm)
Soldering Method Soldering Conditions Package peak temperature: 260 C or below, Time: 30 s. Max. (at 210C or higher), Count: three times or less, Exposure limit: 7 days Note3 (after that, prebake at 125C for 10 to 72 hours) Products packed in a medium other than a heat-resistance tray (such as a magazine, taping, and non-heat-resistance tray) cannot be baked. Partial heating Pin temperature: 300C Max., Time: 3 s. Max. (per pin row) Recommended Condition Symbol Infrared reflow IR60-107-3
Notes 1. Lead-free product 2. High-thermal-resistance product 3. After opening the dry pack, store it at 25 C or less and 65 % RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
64
Data Sheet S16021EJ2V0DS
PD64084
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
65
Data Sheet S16021EJ2V0DS
PD64084
Purchase of NEC Electronics l2C components conveys a license under the Philips l2C Patent Rights to use these components in an l2C system, provided that the system conforms to the l2C Standard Specification as defined by Philips.
* The information in this document is current as of March, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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